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this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. july 2014 docid026157 rev 4 1/85 HM301D diagnostic-quality acquisit ion system for bio-electric sensors and bio-impedance measurements datasheet - preliminary data features ? 3 biopotential acquisition channels with integrated analog high pass filters ? 1 bio-impedance measurement channel with 2- or 4-wire measurement ? digital iq demodulation ? integrated configurable digital filtering and preprocessing ? pacemaker pulse acquisition with embedded detection function (down to 0.1 mv impulse amplitude) ? input connection matrix allows support for different cable configurations ? spi daisy chain supports up to 4 ics connection ? programmable analog gain: 8, 16, 32, 64 ? low supply voltage: 1.62 v to 3.6 v ? input referred noise: 6 v pp (300 hz bw, g=64) ? maximum data rate: 125 ksps per channel ? less than 1 ma/channel at full bandwidth and resolution ? dc and ac lead-off detection ? right leg driver (r ld), wilson common terminal (wct) and shield driver (sd) ? clock reconfigurability ? built-in ring oscillator (5% accuracy) ? built-in crystal oscilla tor (0.1% accuracy) ? external clock ? low external component count architecture ? allows compliance with medical standards ansi/aami ec11, ansi/aami ec13 and iec60601-2-27 ? emi tolerant applications ? ecg (electrocardiogram) ? carts for clinical environments ? bedside monitoring ? holter monitors ? automated external defibrillator (aed) ? eeg (electroencephalogram) ? emg (electromyography) ? wearable remote monitoring ? medical equipment lga 40 l (6 x 6 mm) table 1. device summary order code biopotential channels bio-impedance channel marking package packaging HM301Dl 3 yes HM301D lga 6x6 40l tray www.st.com
contents HM301D 2/85 docid026157 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 input connection matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 biopotential channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 analog section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.3 high resolution low bandwidth signal path (hrlb) . . . . . . . . . . . . . . . . 21 6.3.4 low resolution high bandwidth signal path (lrhb) . . . . . . . . . . . . . . . . 21 6.4 lead off detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 dc contact check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4.2 ac contact check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5 impedance channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5.1 analog section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5.2 digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.6 drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6.1 right leg driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6.2 shield driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6.3 wilson common terminal (wct) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.7 tm and rst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.8 digital machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.8.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.8.2 sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.8.3 boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.8.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
docid026157 rev 4 3/85 HM301D contents 85 6.8.5 ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8.6 measure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8.7 fast recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.9 gpio configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.10 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.10.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.10.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.10.3 daisy chain spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.10.4 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11 power supply voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.12 registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.12.1 application settings (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.12.2 output flags (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.12.3 data registers (re adable only if meas_mode = 1) . . . . . . . . . . . . . . . . 61 6.13 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.13.1 case 1: complete processed data - 4x packet . . . . . . . . . . . . . . . . . . . . 70 6.13.2 case 2: pre-filtered data out - 3x packet . . . . . . . . . . . . . . . . . . . . . . . . 71 6.13.3 header description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.14 data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.15 data ready operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.1 dc offset removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.2 multi-chip configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3 supported ecg configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
list of tables HM301D 4/85 docid026157 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. input-referred noise (v rms /v pp ) / 3 v analog supply 1 . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. input connection matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. pad connection settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. biopotential channel gain and idr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. digital gpio output signals (dgio0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. digital gpio output signals (dgio1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. digital gpio output signals (dgio2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. digital gpio input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. read command bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16. write command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. spi slave timings (iovdd = 1.8 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. psmon_out signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 19. registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 21. data registers (readable only if meas_mode bit is 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 22. set0 ch_enable (addr 27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 23. set1 pm_sel (addr 28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 24. set 2 avg_ctrl (addr 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 25. set3 incon_hcsel_1 (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. set4 incon_hcsel_2 (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. set5 incon_hcsel_3 (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 28. set6 incon_avg_1 (2dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 29. set7 incon_avg_2 (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 30. set8 incon_rld (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 31. set9 cck_en_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 32. set10 cck_en_2 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 33. set11 cck_cur (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 34. set12 cck_trsh (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 35. set13 hc_ana_ctrl (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 36. set14 imp_ana_ctrl (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 37. set15 ecg_digfilt_ctrl (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 38. set16 pm_digfilt_ctrl (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 39. set17 hc_digfilt_ctrl (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 40. set18 hc_hpfana_ ctrl (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 41. set19 rld_ctrl (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 42. set20 recovery_time (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 43. set21 pmd_trsh (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 44. set22 filter_swtime (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 45. set23 digio_io (40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 46. set24 imp_cur_en (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 47. set25 digio12_sel (45h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 48. set26 digio0_sel (46h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
docid026157 rev 4 5/85 HM301D list of tables 85 table 49. out_flag0 (47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 50. out_flag1 (48h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 51. ecg1_dataout_1 (49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 52. cg1_dataout_0 (4ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 53. ecg2_dataout_1 (4bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 54. ecg2_dataout_0 (4ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 55. ecg3_dataout_1 (4dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 56. ecg3_dataout_0 (4eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 57. ecg12_dataout_1 (4fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 58. ecg12_dataout_0 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 59. ecg23_dataout_1 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 60. ecg23_dataout_0 (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 table 61. ecg31_dataout_1 (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 table 62. ecg31_dataout_0 (54h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 table 63. pm1_dataout_1 (55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 64. pm1_dataout_0 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 65. pm2_dataout_1 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 66. pm2_dataout_0 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 67. impedance_phase_ac_dataout_1 (59h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 68. impedance_phase_ac_dataout_0 (5ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 69. impedance_squaring_ ac_dataout_1 (5bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 70. impedance_squaring_ ac_dataout_0 (5ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 71. impedance_phase_dc_d ataout_1 (5dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 72. impedance_phase_dc_d ataout_0 (5eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 73. impedance_squaring_ dc_dataout_1 (5fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 74. impedance_squaring_ dc_dataout_0 (60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 75. contact_check_dataout_1 (61h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 76. contact_check_dataout_0 (62h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 77. data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 78. base pocket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 79. data packet out with 3 HM301D in chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 80. pre-filtered data out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 81. header packet bits description in 4x packet case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 82. header packet bits description in 3x packet case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 83. c_data packet description bits configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 84. contact check and overflow c_data vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 85. hrlb data-out sampling frequency vs low pass filt er cut-off frequency. . . . . . . . . . . . . . . 74 table 86. lrhb data-out sampling frequency vs low pass filt er cut-off frequency. . . . . . . . . . . . . . . 74 table 87. impedance data-out sampling frequency vs low pass filter cut-off frequency. . . . . . . . . . . 75 table 88. common ecg configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 89. lga 40l (6 x 6 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 90. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
list of figures HM301D 6/85 docid026157 rev 4 list of figures figure 1. HM301D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. biopotential channel block schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. first decimation filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5. hrlb digital signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. lrhb signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. contact check architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. impedance channel architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. impedance channel digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. avg buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. wct buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. state machine for packets streaming mode (meas_mode = 0) . . . . . . . . . . . . . . . . . . . . . 30 figure 13. state machine for packets streaming mode (meas_mode = 1) . . . . . . . . . . . . . . . . . . . . . 31 figure 14. single byte reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15. double byte reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16. single byte writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17. example of daisy chain spi connection with 3 hm30 1d . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18. example of daisy chain spi writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19. example of daisy chain spi readin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21. spi communication - packet data streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 22. ecg_out registers data reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 23. maximum dc offset remo val . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 24. example of chain connection: standard 12-lead ec g . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 25. package outline for lga 40l (6 x 6 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
docid026157 rev 4 7/85 HM301D description 85 1 description the HM301D is a highly integr ated diagnostic-quality biopotent ial acquisition system with 3 differential channels. multi master/slave co nfiguration supports up to 16 channels of simultaneous sampling (12 biopotential acquisi tions and 4 bio-impedance channels). a fully integrated high-pass filter removes the half-ce ll dc value to enable the channels to work with the ac component only. each channel provides high resolution and low noise conversion of biopotential signals up to 10 khz. the input connection circuit ma trix guarantees maximum flexib ility in terms of electrode cables and connectors. the HM301D includes a dedicated impedance measurement channel that can be used to measure both body impedance average value and variation due to respiration. this channel delivers both the real and the imaginary parts of the body and the breathing impedances. the wct circuit and driver block implements the driving functions (right leg driver and shield driver) and the wilson common terminal commonly used in ecg systems. the electrode-to-skin contact is checked by inje cting an ac or dc curren t. a digital filtering and preprocessing (dfp) block implements co nfigurable band-pass filters, iq impedance demodulation and enables specific algorithm implementation for lead-off check and pacemaker detection. the spi interface allows the exchange of da ta with both the microcontroller and other HM301D devices in case of chain connection. full config urability and low power design techniques make it ideal for many applicati ons, including battery-powered devices. high quality recordings are obtained with a small, power-saving system. the 3-channel version is available in a 6 x 6 mm 40-lead lga.
block diagram HM301D 8/85 docid026157 rev 4 2 block diagram figure 1. HM301D block diagram input ma t r i x bi o pot ent i al ch3 chop amplifier+adc dc&ac contact check dr i v e r s rld_comp wct sd vss vss sgnd sgnd avgio xtalin xtalout ckext dvss cs spc sdi sdo vref cl ock dgio0 dgio1 dgio2 tm1 tm0 nvm spi confi g rst rld vref in3n in3p vref in2p in2n vref in1p in1n bi o pot ent i al ch2 chop amplifier+adc dc&ac contact check bi o pot ent i al ch1 chop amplifier+adc dc&ac contact check impedance channel connec t i on cip cin supply mo n i t o r imp. channel current injection filters digital reference voltage por & reset dig filters low bw high res hrlb dig filters low bw high res hrlb dig filters low bw high res hrlb high bw lowres dig filters dig filters high bw lowres mux ana2_out ana3_out ana1_out vdd vdd iovdd dvdd test0 test mu x am17580v2
docid026157 rev 4 9/85 HM301D pin configuration 85 3 pin configuration figure 2. pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 table 2. pin description pin name pin n type description in1p 1 ana in connected to biopotential channel #1 positive input by default. see input connection matrix to change it in1n 2 ana in connected to biopotential channel #1 negative input by default. see input connection matrix to change it vdd 3 ana in analog supply voltage in2p 4 ana in connected to biopotential channel #2 positive input by default. see input connection matrix to change it in2n 5 ana in connected to biopotential channel #2 negative input by default. see input connection matrix to change it vss 6 ana gnd analog ground in3p 7 ana in connected to biopotential channel #3 positive input by default. see input connection matrix to change it in3n 8 ana in connected to biopotential channel #3 negative input by default. see input connection matrix to change it rld 9 ana out connected to right leg driv er output by default. see input connection matrix to change it wct 10 ana out wilson common terminal output rld_comp 11 ana io input of rld buffer. to be used for co mpensation in case of instability of rld loop
pin configuration HM301D 10/85 docid026157 rev 4 avgio 12 ana io average value of electrode signals connected to assp (o) or coming from other chain connected assps (i) sd 13 ana out driver output of shield cables ana1_out 14 ana out channel1 single ended analog output ana2_out 15 ana out channel2 single ended analog output ana3_out 16 ana out channel3 single ended analog output test0 17 ana io used for test purposes. leave float in normal operation vss 18 ana gnd analog ground vdd 19 ana in analog supply voltage vref 20 ana io reference voltage to or from other chain connected assps xtalout 21 ana out crystal pin connection xtalin 22 ana in crystal pin connection sgnd 23 ana gnd analog ground dvdd 24 ana in digital supply voltage ckext 25 dig io clock signal to/from other devices rst 26 dig out por (when tm0 = tm1 = 0) dig in enable (when tm0 = 1, tm1 = 0) tm0 27 dig in configuration pin # 1 tm1 28 dig in configuration pin # 2 dvss 29 dig gnd digital ground sdo 30 dig out spi serial data output iovdd 31 ana in supply voltage for io pins. it provides the voltage to spi and gpios it must be always lower than vdd. sdi 32 dig in spi serial data input cs 33 dig in spi chip select spc 34 dig in spi serial port clock dgio2 35 dig io general purpose digital io dgio1 36 dig io general purpose digital io dgio0 37 dig io general purpose digital io sgnd 38 ana gnd analog ground cin 39 ana out ac current injection negative pin for impedance measurement cip 40 ana out ac current injection positive pin for impedance measurement table 2. pin description (continued) pin name pin n type description
docid026157 rev 4 11/85 HM301D maximum ratings 85 4 maximum ratings note: absolute maximum ratings ar e those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value (1) 1. all values are referred to vss. unit v dd analog supply voltage -0.3 to 4.8 v dv dd digital supply voltage -0.3 to 4.8 v iov dd ios supply voltage -0.3 to 4.8 v analog i/o all analog ios -0.3 to 4.8 v digital i/o all digital ios -0.3 to 4.8 v t op operating temperature range -40 to 100 c t st storage temperature range -65 to 150 c t j maximum junction temperature +150 c esd hbm 2 kv cdm 500 v table 4. thermal data symbol parameter value unit r thja junction to ambient thermal resistance 55 c/w
electrical characteristics HM301D 12/85 docid026157 rev 4 5 electrical characteristics t a = 0 to 70 c, v dd = dv dd = iov dd = 3 v, v ref = 0.7 v, unless otherwise specified. table 5. electrical characteristics symbol parameter test conditions min. typ. max unit general section av dd iov dd dv dd supply voltages 1.62 3.6 v i dd current consumption power down mode 10 ? a 3 channels on, impedance off, rld on, wct on 33.6ma 1 channel on, impedance off, rld on, wct off 1.3 1.6 ma 1 channel on, impedance on, rld on, wct off 2.2 2.7 ma v ih high level input voltage all inputs 0.8 x iovdd v v il low level input voltage all inputs 0.2 x iovdd v v oh high level output voltage all outputs 0.9 x iovdd v v ol low level output voltage all outputs 0.1 x iovdd v biopotential channels v bio- diff differential input voltage signal bandwidth 0.05 hz - 10 khz 0.8/ gain v input impedance signal bandwidth 0.05 hz- 300 hz dc contact check on 50 m ? dc contact check off 50 analog high pass rc filter cut off frequency 0.05 hz input bias current 10 pa input differential bias current 10 pa gain setting 8, 16, 32, 64 v/v total gain error ina+pga+adc+vref 1 % gain match between channels 31.25 0.5 % chopping frequency 31.25 khz
docid026157 rev 4 13/85 HM301D electrical characteristics 85 total accuracy (quantization, linearity, noise) v diff-pp =20mv; gain=64; 10hz 15 v adc resolution ac signal only, dc value removed by high-pass filter 16 bits odr max data rate (internal filters bypassed) after 1 st decimation filter 125 ksps input referred noise signal bandwidth 0.1 hz - 150 hz data rate = 488 hz gain=64 0.6 vrms gain=32 1.1 gain=16 2 gain=8 4.2 cmrr common mode rejection ratio 60hz, 100mv pp 100 db snr signal to noise ratio gain=64, differential input signal frequency 10hz, 10mvpp; vdd=3v hrlb 72 db gain=16, differential input signal frequency 1khz, 40mvpp; vdd=3v lrhb 62 db impedance channel v zc-diff differential input voltage 0.8/ gain v gain setting 8, 16, 32, 64 v/v accuracy (quantization, linearity, noise) dc impedance range [50, 5k] ? , point calibration 50 ? 1.5 % adc resolution 16 bits impedance measurement noise 0.05 hz to 1 hz filter, 31.25 khz modulation frequency, 100 ohm baseline resistance 20 ? a with gain = 64 100 m ? total phase shift 115 deg gain error 0.1 % impedance channel current injection injection current 5, 10, 20 a sink/source current matching 15 na current injection frequency 31.25 khz rld amplifier integrated noise bandwidth 0,05hz-300hz 20 vrms table 5. electrical ch aracteristics (continued) symbol parameter test conditions min. typ. max unit
electrical characteristics HM301D 14/85 docid026157 rev 4 gain f=50hz 50 db output voltage swing ilim 880 na v ss + 0.325 v dd -0.35 v sink/source current vdd = 3v 11 a current consumption 90 a wct amplifier integrated noise bandwidth 0,05hz-300hz 1.5 vrms gain bandwidth product 0.5 mhz gain 1v/v sink/source current 33/18 a output voltage swing v dd =1.8v v ref -0.5 v ref + 0.5 v shield amplifier integrated noise bandwidth 0.05hz-300hz 8 vrms gain 1v/v bandwidth 490 hz sink/source current 10 a output voltage swing high level, v dd =1.8v v ref - 0.63 v ref + 0.59 v current consumption 11 a dc contact check dc current 25, 50, 100, 200 na dc current accuracy t a =25c 5 % comparator threshold t a =25c vss + 102 vdd- 102 mv step threshold 102 mv ac contact check injection current 5, 10, 20 a sink/source current matching na current injection frequency see hc_curinj_freq bit 2.5, 5 khz voltage reference v ref reference voltage v dd =3.3v; psmon_sel_r=1 1.0 v accuracy 1 point temperature calibration; t a =25c 0.15 % table 5. electrical ch aracteristics (continued) symbol parameter test conditions min. typ. max unit
docid026157 rev 4 15/85 HM301D electrical characteristics 85 integrated noise bandwidth 0.05hz-300hz 15 vrms ring oscillator frequency 2.00 mhz accuracy t a =25c 2 % t a =0 ? 70c 10 % current consumption 12 a duty cycle 40 60 % crystal oscillator frequency 4 mhz crystal, internally divided by 2 2.00 mhz accuracy t a =0 ? 70c 0.1 % current consumption 68 a duty cycle 40 60 % external clock frequency 2.00 mhz low level signal 0.1 x iovdd v high level signal 0.9 x iovdd v duty cycle 40 60 % table 5. electrical ch aracteristics (continued) symbol parameter test conditions min. typ. max unit table 6. input-referred noise (v rms /v pp ) / 3 v analog supply 1 output data rate (hz) -3 db bandwidth (hz) gain = 8 gain = 16 gain = 32 gain = 64 1953 600 6.2/41.5 3.1/20. 2 1.56/11.3 0.931/6.8 976 300 5.2/37 2.7/18.7 1.39/10.1 0.81/6.4 651 200 5.5/36 3.78/22.1 1.3/8.4 0.841/5.3 488 150 4.2/28 1.98/14.4 1.1/7.17 0.615/4.2 325 100 4.0/27.1 3.0/17. 7 1.01/6.8 0.715/4.5 244 75 3.1/20 1.7/11.1 0.93/5.87 0.554/3.8 163 50 3.1/19.5 1.59/10.04 0.83/6.1 0.7/3.4 122 37 2.4/15.8 1.2/8 .1 0.76/4.5 0.46/2.6 81 .5 25 2.5/15.5 1.55/8.39 0.78/4.5 0.47/2.6
detailed description HM301D 16/85 docid026157 rev 4 6 detailed description 6.1 overview the HM301D includes three biopotential channels with bio-impedance channel. even if specifically designed for ecg application, the HM301D is suitable to collect any biopotential signal including eeg and emg ones. the biopotential channels measure both the incoming ecg/eeg/emg and pacemaker (pm) signals and provide both analog (on anax _out pins) and digital (send out over spi) outputs. an additional feature of each biop otential channel is the contact check whose purpose is to notify the user when the electr ode contact has become poor. this is a dc and ac check and gives an indication on the electrode contact resistance. the architecture of the biopotential channel is described in more detail in section 6.3 . the bio-impedance channel provides an accurate measurement of the body and electrode impedance. an ac-current is injected at a configurable frequency through the body; the resulting ac-voltage is measured and processed. in order to get rid of the impedance given by the defibrillator protections resistors, a 4 wires measurement (force and sense) can be implemented by connecting two dedicated electrodes to the injection pins (cip and cin). section 6.5 provides more details about the architecture of this channel. the input connection circuit allows the use of several kinds of cable connectors based on the application. any of the input signals on inxy, (x = 1, 2, 3; y = p, n) can be switched to any of the 3 biopotential channel inputs. also th e output of the rld can be connected to any inxy. the drivers block (see section 6.6 ) provides specific reference signals required in both standard ecg applications and multiple ch ip configuration (e.g. wct, rld, sd). the wilson common terminal circuit (see section 6.6.3 ) averages the signals present on the r,l and ll electrodes and serves as a reference voltage for unipolar measurements (e.g. ecg: v1,v2?v6). the right leg drive (see section 6.6.1 ) sets a proper dc-voltage at the input of the HM301D by connecting the rld output to the rl electrode on the body. rld_comp pin allows for the use of an external compensation network, if needed. in case of shielded cables a shield driver (see section 6.6.2 ) is provided. in order to enable applications with a large nu mber of electrodes (e.g. r, l, ll, v1, v2, v3, ?) it is possible to use the HM301D in a mult iple chip configuration: up to four devices can be connected using a daisy chain spi. in this case, all the avgio pins are tied together in order to provide the overall common mode signal of all system electrodes. the HM301D contains a dedicated digita l signal processing with the following functionalities: ? user configurable signal filtering: low pass and high pass; ? simultaneous processing of both high resolution/low bandwidth (hrlb) and high bandwidth/low resolution (hblr) signals (e.g. ecg and pacemaker); ? iq impedance demodulation (real and imaginary part); ? standard spi communication; ? device configuration settings;
docid026157 rev 4 17/85 HM301D detailed description 85 the supply monitor gives a 2-bit indication of the battery status. an accurate voltage reference is embedded. the rst pin can be configured to provide a power-on-reset signal or to accept an external enable signal from the mcu. the clock circuit offers the maximum configurability: ? embedded ring oscillator; ? crystal oscillator; ? external clock; 6.2 input connection matrix the input connection circuit allows the use of several kinds of connectors. anyone of the input pins inxy (x = 1, 2, 3; y = p/n) can be switched to any of the 3 biopotential channel inputs and to the rld driver output. since the signals of the input pins can chang e according to the connector used, also the connections of the avg buffers block must be cha nged. this is done by setting the right bits according to the following table: for all the registers the follo wing configuration is valid: table 7. input connection matrix setting description default inputcon_in1p_hcsel_r<2:0> connect input pad in1p to one of the 6 health channel inputs 111 inputcon_in1n_hcsel_r<2:0> connect input pad in1n to one of the 6 health channel inputs 111 inputcon_in2p_hcsel_r<2:0> connect input pad in2p to one of the 6 health channel inputs 111 inputcon_in2n_hcsel_r<2:0> connect input pad in2n to one of the 6 health channel inputs 111 inputcon_in3p_hcsel_r<2:0> connect input pad in3p to one of the 6 health channel inputs 111 inputcon_in3n_hcsel_r<2:0> connect input pad in3n to one of the 6 health channel inputs 111 inputcon_avg1_r<2:0> connect input avg bu ffer1 to any of the 6 input pads inxy (x=1,2,3;y=p/n) 111 inputcon_avg2_r<2:0> connect input avg bu ffer2 to any of the 6 input pads inxy (x=1,2,3;y=p/n) 111 inputcon_avg3_r<2:0> connect input avg bu ffer3 to any of the 6 input pads inxy (x=1,2,3;y=p/n) 111 inputcon_avg4_r<2:0> connect input avg bu ffer4 to any of the 6 input pads inxy (x=1,2,3;y=p/n) 111 inputcon_rld_sel_r<2:0> connect the rld out to any of the inputs pads inxn/p, for x=1,2,3. whatever is the bits configuration, the rld out is always connected to rld pin. 111
detailed description HM301D 18/85 docid026157 rev 4 the nomenclature used in the pin description an d pin configuration is referred to the default setting of the connection matrix. the rld driver output can be connected to any of the inxy pads but, in any case, it is always connected to rld pin. 6.3 biopotential channel figure 3. biopotential channel block schematic figure 3 shows the architecture of one biopot ential channel. each channel can be selectively switched on/off. the high resolution low bandwidth signal is available in ecgx_datao ut registers while the a low resolution high bandwidth signal is available in the output data packet. 6.3.1 analog section the input signal first passes through the analog high-pass filter with corner frequency of 0.05 hz, in this way the dc component is re moved maintaining the integrity of the signal even at low frequencies. table 8. pad connection settings bits configuration pad connection 000 in1p 001 in1n 010 in2p 011 in2n 100 in3p 101 in3n 110 not connected 111 not connected ecg hpf: 0.05 ? 5 hz lpf: 25 ? 300 hz gain error correction decimation filter gain error correction pm hpf: 0.05 ? 1 khz lpf: 5k ? 10 khz single ended high speed 2 order sdadc overflow to digital pm threshold ina pga hpf ecg pm pmd chop ch1 ch2 ch3 mux chop lpf vref am17596v1
docid026157 rev 4 19/85 HM301D detailed description 85 due to the very low cut- off frequency, the start-up time of the channel could be very long. in order to avoid this, the HM301D goes in recovery mode in which the high pass filter cut-off frequency is changed to higher values. at start-up or after overvoltage condition, the cut-off starts from 5 hz , then goes to 0.7 hz and finally to 0.05 hz . the 5 hz cut-off frequency has a very fast settling speed and will set the common mode level of the instrumentation amplifier. by default, the switching time between the different cut-off frequencies is se t at 200 ms but it can be changed in the set22 register. the recovery mode acts both on analog and digital high pass filters, but the digital filter stops at the fr equency which has been set in the hc_dig_pmhpf_sel_r bits. if the recovery mode is off, the cut off frequency of this analog high pass filter can be changed at application level by changing the hc[1,2,3]rhpf_sel_r bits. after the high pass filter, the signal is chopped and fed to the amplification stage (instrumentation amplifier and programmable gain amplifier). the signal is filtered by a 110 khz low pass before being supplied to the adc. a differential to single-ended block makes t he analog signal available at the pins ana[1,2,3]_out. the output voltage of the diff erential to single-ended block is equal to: equation 1 where v ref is 0.7 v or 1 v the adc is a 2 nd order 16bits ?? working at 2 mhz. since the dc component of the signal has been already removed by the high-pass filter , the adc is sampling just the useful part of the signal so that the 16bits provide a very good resolution for any biopotential signal. the bit stream is then processed in the digital domain. the following parameters of the analog portion of the biopotential channel can be modified through the spi interface: ? ia gain: 8, 16 (hc_ina_gain_r); ? pga gain: 1, 2, 4 (hc_pga_gain_r); ? chopping frequency: 31.2 khz; ? cut-off frequency of the analog high pass filter (hc[1,2,3]rhpf_sel_r); table 9. biopotential channel gain and idr ia gain pga gain idr [mv] 81200 82100 16 2 50 16 4 25 ref inxn inxp v v v gain out se diff ? ? ? ? 2 _ 2
detailed description HM301D 20/85 docid026157 rev 4 6.3.2 digital section figure 4. first decimation filter the channel converts two signals to the digital domain: a high resolution low bandwidth (hrlb) and a low resolution high bandwidth (lrhb), for example the ecg and the pacemaker signals respectively. their frequen cy content is 0.05-300 hz and 0.05-10 khz. while the hrlb are available for all the thr ee biopotential channels, there are two lrhb signal paths which can be connected to any of the three biopotential channels. this is configured through the pmd_sel_r bits. for both hrlb and lrhb signals, the digitized data values are in binary one?s complement format. the analog input value is calculated acco rding to the following formula: equation 2 where ? sign is plus if msb is 0, minus if msb is 1; ? data10 is the decimal value of the 15 lsbs if msb is 0 or of the 15bits one?s complement if msb is 1; ?v ref = 0.8 v; ? gain = ia_gain x pga_ga in is the total gain; the first digital block is a decimation filter. starting from the 2 mhz 1bit stream provided by the ?? modulator, a decimation rate of 16 is taken. the first decimation stage is then used for both the two signal paths. the sampling fr equency is 2 mhz and the output is a 125 khz 12 bits digital signal. since the adc is implemented as a 2 nd order delta-sigma, the digital stream has 2 nd order noise shaping. this must be filtered adequately to prevent aliasing. to obtain this, a 3 rd order cic-filter was chosen. this filter has an attenuation of -0.274 db (3%) at 10 khz and -0.2 mdb at 300 hz. the output wo rd length is 12 bit which can be provided to the spi interface by configuring the bit dataou t_prefilter_en in the set13 register. in this way all the subsequent filters are bypassed. am17583v1 high speed 2 rd order ds adc first decimation filter osr = 16 1 b 12 b bw > 10 khz fs = 2 mhz fs = 125 khz hr lb (0.05 ? 300 hz) lr hb (0.05 ? 10 khz) 1 16 10 2 ? ? ? ? ? data gain v v v ref inxn inxp
docid026157 rev 4 21/85 HM301D detailed description 85 6.3.3 high resolution low band width signal path (hrlb) figure 5. hrlb digital signal path after the first decimation filter, a second de cimation is performed in order to reduce the sampling frequency and, in the same time, to cut the high frequency signal part. the second decimation for hrlb signal is fixed to 32 a nd the output sampling frequency is 3.906 khz. after that, a high pass filter is implemented. the -3 db cut-off frequency is variable with 6 possible values: 0.05, 0.5, 0.7, 1, 2 and 5 hz (hc_dig_ecghpf_sel_r<0:2>). after the hpf, a fir filter with selectable bandwidth of 25, 37, 50, 75, 100, 150, 200 and 300 hz (hc_dig_ecglpf_sel_r < 0 : 2 >) is implemented. at the end, a furthe r decimation by 2 is inserted. finally, the output signal is sent to the spi block. the following parameters can be set through the spi interface: ? low pass filter cut-off frequency: 25, 37.5, 50, 75, 100, 150, 200, 300, 600 hz (hc_dig_ecglpf_sel_r); ? high pass filter cut-off frequency: 0.05, 0.5, 0.7, 1, 2, 5 hz (hc_dig_ecghpf_sel_r); ? cut-off start frequency of the high pass digital filter for the start-up procedure (hc[1,2,3]_dig_hpf_sel_r). active on ly when recovery mode is off. 6.3.4 low resolution high ba ndwidth signal path (lrhb) the lrhb signal path takes the same signal of 12 bits 125 khz, coming from the 1st decimation filter, as input. linear phase response is an important parameter. this can only be achieved by using fir filter s. implementing fir filters to filter a 5 khz with a sampling frequency of 125 khz will require a lot of taps in the filter. as with the hrlb path low pass filter, a decimation step is performed to lower the sampling frequency so to decrease the required taps in the fir filters. the lrhb signal can be provided with differ ent cut off frequencies for low and high pass filters. as shown in figure 6 , the configuration of the digital blocks is changed in case of 5 khz and 10 khz low pass cut off frequencies. a decimation step of 2 is done for the 10 khz case and a decimation of 4 for the 5 khz one, in this way the same fir filter with only 4 ta ps is used in both cases. implementing this decimation step with a good pass-band char acteristic can be achieved with a cic decimation filter. for the 10 khz low pass filter case, the fir filt er follows the first decimation filter, then a new decimation by 2 and finally the iir high pass filter. for the 5 khz case, the fir and iir filters are swapped each other and, the decimation rate of the first filter is doubled. am17584v1 high pass filter 0.05; 0.5; 0.7; 1; 2; 5 hz fir filter bw = 25; 37; 50; 75; 100; 150; 200; 300 16 b 16 b decimation osr = 2 fs = 3.906 khz fs = 0.163 ?1.953 khz 16 b fs = 82 ? 976 hz spi 16 b second decimation filter osr = 32 fs = 3.906 khz hr lb (0.05 ? 300 hz) 12 b
detailed description HM301D 22/85 docid026157 rev 4 figure 6. lrhb signal path the following parameters can be set through the spi interface: ? low pass filter cut-off frequency: 5, 10 khz (hc_dig_pmlpf_sel_r); ? high pass filter cut-off frequency: 0.05, 0.7, 1, 5,1000 hz (hc_dig_pmhpf_sel_r); ? connection of the two lrhb signal paths to any of the three biopotential channels (pm_sel_r); the lrhb signal path provides also a signal amplitude detection functi on. this function is useful as pacemaker detection (pmd) in ecg systems where reduced odr, fewer mips for the host and low power consumption are key fe atures. integrated hardware detection of the pacemaker pulse allows the device to meet these requirements. the 9 most significant bits without sign of the lrhb (16 bit) are compared with a user selectable threshold of 9 bit (hc_pmd_thres_r). when the threshold value is higher than the absolute value of the lrhb signal the output signal (pmd) is asserted high. two pmd signals are available at dgio1 and dgio2 ou tputs. in ecg application these signals provide the pace maker detection signal. since the comparison is done at digital level, the threshold value must be changed according to the gain setting. for example, if a 0.2 mv value must be dete cted at the input of the channel and the threshold is set at 000000001, since one lsb of the adc is 24 v, the 0.2 mv represents the 6 th bit of the lrhb word with a gain of 8 or the 9th bit with a gain of 64. since the comparison is done with the 9 msbs, in the fi rst case the pmd signal will be always low while in the second case the pmd will change in the same way as the 9th bit of the lrhb word. 6.4 lead off detection during ecg measurement and especially during a long period of monitoring, the electrode to skin contact check is needed in order to guarantee an adequate impedance value for a good signal acquisition. the HM301D provi des two types of contact check: dc and ac am17585v1 decimation filter osr = 2 fir filter bw = 10 khz decimation by osr = 2 16 b 16 b 16 b fs = 62.5 khz iir filter bw = 0.05 hz; 0.7 hz; 1 hz; 5 hz; 1 khz fs = 62.5 khz fs = 31.25 khz 16 b fs = 31.25 khz spi 12 b dec filter by 16 fs = 31.25 khz decimation filter osr = 4 decimation by osr = 2 16 b 16 b 16 b fs = 31.25 khz fs = 31.25 khz fs = 15.625 khz 16 b fs = 15.625 khz spi 12 b dec filter by 16 iir filter bw = 0.05 hz; 0.7 hz; 1 hz; 5 hz; 1 khz fs = 15.625 khz fir filter bw = 5 khz 16 b 12 b (a) 10 khz low pass filter (a) 5 khz low pass filter
docid026157 rev 4 23/85 HM301D detailed description 85 figure 7. contact check architecture 6.4.1 dc contact check one current source and one current sink are connected at each of the 6 inputs of the biopotential channels. two comparators are also connected at each pin. each of the 6 current sources can be activated by setting the in[1-3]_contact_pdp_r bits while the 6 current sinkers are activated by setting the in[1-3]_contact_pdn_r bits. according to the electrode configuration, the proper current source /sink must be activate d. a small selectable current (25, 50, 100, 200 na) is injected by the current source through one electrode and body of the patient and back into the HM301D through another electrode where the right current sinker is turned on and having the same current value setting. this current generates a voltage drop that is detected by the comparators connected to each pin. the comparator threshold is also selectable in a different way for the high side comparators (cck_threshp_sel_r) a nd for the low side comparators ( cck_threshn_sel_r) . there are 16 possible comparator threshold values. the maximum current mismatch between one current source and one current sinker is 10%, in this way the dc current going to the body is very small. 6.4.2 ac contact check the ac contact check is based on the same principle of the dc contact check. in this case, an ac current (square wave) with a 2.5 khz or 5 khz (hc_curinj_freq_r) frequency is injected through the electrodes. the possible current values are 5, 10 or 20 a. the quality of the electrode contact will be then evaluated by the host m cu by analyzing the injected frequency component in the lrhb signal. for each biopotential channel the ac current source connected to the positive pin of the differential input is 180 out of phase with the one connected to the negative pin. in this way the current flows through the body and returns to the negative pin. when the contact am17586v1 vref vref avg (la, ra) vdd_dc_cc threshold + - + - + - vss_dc_cc threshold + - 0 0 vdd vdd vdd 0 ina inx,y inx,y electrode ra la rl rld dc contact check comparator. dc contact check comparator. electrode electrode
detailed description HM301D 24/85 docid026157 rev 4 between two electrodes, each connected to the positive or negative inputs of two different channels, has to be checked, then it is necessary to reverse the phase of one of two involved ac current generator. the hc[1-3]_ph aserev_r bits allow doing it so that any electrode configuration can be implemented. the ac current generator is enabled by settin g the relative hc[1-3]_curinj_en_r bit. in addition, by setting the hc_curinj_en_ext bit it is possible to enable/disable the ac current generators thro ugh an external logic signal applied to the digio2 pin. this signal will be and-ed with the hc[1-3]_ curinj_en_r bits, so that only t he enabled current generators will be turned on. 6.5 impedance channel the goal of the impedance channel is to measure the impedance of the body and to measure the variation of this impedance due to the respiration. in reality the measured impedance won't be the impedance of the body alone but the series connection of the body with the board protections, the 2 electrodes and with skin and gel impedances. these values must be taken into account when reading the impedance values of HM301D. the impedance circuit detects impedance values by injecting a high frequency square wave ac current through the cip and cin pins and monitoring the resulting voltage ( figure 8 ). high frequency is imposed both for safety reasons and due to the electrodes' band pass. to avoid electrode polarization the average injected current is minimized. figure 8. impedance channel architecture the body impedance is used as an indicator to determine biological parameters, such as those used for galvanic skin response evaluation and patient fluid status check. furthermore, in automated external defibrillator (aed) applications, body impedance evaluation is needed in order to deliver the proper amount of energy to the patient. this function has been designed considering applicati on-specific electrodes (i.e. with polarity). the modulated impedance (ac impedance) measurement principle is based on bio- impedance measurement on the patient's thorax and allows the measurement of respiration concurrently with the ecg and pacemaker measurements using two standard ecg electrodes. the time variation of body impedance due to resp iration and chest movement is measured. this allows breath rate evaluation and provides information about movement artifacts that can affect ecg measurement. am17596v1 bpf 20 ? 50 khz lpf 1 hz decimation filter demodulator high speed 3 order ? adc overflow to digital ina pga hpf zdc_r zac_r lpf from health channel 1 gain =8,16 gbw>2mhz gain =1,2,4 gbw>2mhz fc<0.1khz gain =1 fc=250 khz lpf 1 ? 20 hz hpf 0.05 hz lpf 1 hz lpf 1 ? 20 hz hpf 0.05 hz zdc_i zac_i analog digital bw>10khz fs =2 mhz
docid026157 rev 4 25/85 HM301D detailed description 85 the impedance is measured by the injectio n of an ac current at 31.25 khz and by measuring the resulting voltage across it. th e current value can be chosen among three different values: 5, 10 and 20 a. since this cu rrent is injected using different pins from the ones where the voltage is measured, a 4 wire measure (force and sense principle) is implemented. even if unpractical in real applications, usin g 4 different electrodes is really helpful to improve the accuracy of the impedance measurement. anyhow using only 2 electrodes but separating the pcb path of fo rce and sense until the cable connector, will bypass all the impedances of the application (protections, pcb tracks, etc) which usually have higher values than the ones that must be measured. fo r example, in ecg systems, the defibrillator and esd protection resistors could be as high as 25 k ? , while the measured body resistance is ~ 0.5 k ? . the impedance channel differential input is connected to the same input of biopotential channel 1 (see figure 1 ). the impedance channel outputs a real part and an imaginary part of the modulated impedance. this is obtained by iq demodulation in the digital part of the channel which introduces additional gain and phase shift. 6.5.1 analog section all analog blocks of the impedance channel are the same as their counterparts of the biopotential channel except for the low pass f ilter which has now a cut-off frequency of 250 khz. another difference is the adc which is now a 3 th order cascaded (2-1) low pass-delta- sigma. a second order converter plus an extr a stage that converts the quantization noise are implemented. theref ore the adc will have 3 th order noise shaping. the following parameters can be set through the spi interface: ? current injection frequency: 20, 25, 31, 35, 41, 45, 50 khz (imp_curinj_freq_r); ? current injection va lue: 5, 10 20 a (imp_curinj_cur_r); ? ia gain: 8, 16 (imp_ina_gain_r); ? pga gain: 1,2, 4 (imp_pga_gain_r); 6.5.2 digital section figure 9 shows the 3 rd order ?? adc followed by the filters in the impedance channel. the signal is first decimated and band pass filtered so to get sampling frequency of 4 times the signal frequency. an iq-demodulator splits t he signal in a real (i) and imaginary (q) component. the result is again decimated before a final high pass filter at 0.05 hz and low pass filter at 20 hz or 1 hz. the high pass filter is used to extract the ac component in combination with the 20 hz or (after extra de cimation) 1 hz low pass filter. for the dc- component, only the 1 hz low pass filter is used, without the high pass filter.
detailed description HM301D 26/85 docid026157 rev 4 figure 9. impedance channel digital section the following parameters can be set through the spi interface: ? digital low pass filter cut-off frequ ency: 1 or 20 hz (imp_dif_lpf_sel_r) 6.6 drivers the global architecture fo r the drivers is shown in figure 10 . the drivers operation is specifically designed for ecg systems. in part icular the wct (wilson common terminal) is used in unipolar ecg systems, while rld is the right leg driver for ecg which allows reducing system disturbances. the shield driv er is used in case of shielded cable. an important role is played by the four avg buffers. the positive inputs of these buffers are connected to any of the inxy pins by programming the input connection matrix (inputcon_avg[1-4]_r). in this way, the average value of any combination of the biopotential channels can be created. the output of the av g buffers is fed to the shield driver and rld driver. each of the four avg buffers can be turned on/off by setting the avg_en_buf[1-4]_r bit. it is important to turn on only the avg buffers used because the summing resistors will be programmed according to the numbers of avg buffers which are on. in addition the right number of avg buffers used must be written in the avg_numb_buf_r bits. this number will represent the total number of avg buffers used also in the case of multiple connections of HM301D chips, wh ere all the avgio pins are tied together. the topology of the drivers is based on the following considerations: it should not load the input signal. therefore the electrode inputs are buffered with unity gain buffers. the unipolar measurements should have sim ilar accuracy as the bipolar measurements. this basically means that the total noise contribution of the 3 unity gain buffers must be smaller than the total noise contributi on of the entire biopotential channel. the bandwidth of the wct circuit must be enough to not generate too much delay. am17612v1 ac component ? adc post-processing first decimation filter osr = 25 5 b 16 b fs = 2 mhz bpf fc = fs /4 iq demodulation 16 b q16 b i16 b 2 decimation filter hpf fc=0.05hz decimation and lpf i q decimation and lpf q16 b i16 b fs = 4*fm f m = modulation frequenc y times temp = 1/fs fs = 4*fm dc component i16 b i16 b q16 b q16 b
docid026157 rev 4 27/85 HM301D detailed description 85 figure 10. avg buffers 6.6.1 right leg driver the human common mode must be driven in order to set it at the HM301D reference. the driver is connected to the right leg of the patient by means of an electrode, and the effect of the rld is to reduce the effective electrode impedance. when the ic s are chain-connected only the rld of one chip will be connected to the electrode, because the total average is already performed by the avg buffers. applications without the right leg electrode are considered and, in these cases, rld can be used to drive the electrode signals by means of 2 external resistors. the rld_comp pin allows the connection of an external compensation network in case of need for the rld loop stabilization. 6.6.2 shield driver if shielded electrode wires are used, the shield mu st be driven in order to reject interference from the main. the shield is driven to the average value of all the electrode signals (also considering multi chip configuration). 6.6.3 wilson common terminal (wct) wct is the standard potential used to evaluate precordial leads in ecg applications. this potential is defined and evaluated as the average of right arm, left arm and left leg electrode potentials. this value is available on a dedicated pin as an analog signal. the wct buffer needs to be fast enough to have a low delay. the bandwidth of the wct driver is 0.5 mhz at least, but since the wct output goes off-chip, it has to steer the input of rld_out vref + - + - + - + - + - - + inxy inxy inxy inxy avg block avgio rld driver - + shield driver sd avg1 avg2 avg3 avg4 open/closed loop rld_cut_r bit (set 19 reg.) rld_comp external network for rdl loop stabilization rld_comp avgio gams1103141035sg
detailed description HM301D 28/85 docid026157 rev 4 the biopotential channels and the load of the pcb connections. the average is made with 3 times 100 k ? resistors. the positive inputs of the 3 wct buffers are tied to inputs of the first three avg buffers (avg1,2,3). so the inputcon_avg[1-3]_r bits determine where the three inputs of the wct buffers are connected. figure 11. wct buffer 6.7 tm and rst pin configuration the HM301D rst pin can be configured as input and output by the tm pins. when tm0 and tm1 pins are both grounded, the rst pin is configured as an output and the rst pin outputs a por signal. if tm1 is grounded and tm0 is connected to dvdd the rst pin is configured as an enable input. when pulled high, all on chip circuitry is powered up when asserted low the device goes in sleep. am17633v1 + - + - + - + - inxy inxy inxy inxy avg block avgio + - + - + - avg1 avg2 avg3 avg4 wct block wct
docid026157 rev 4 29/85 HM301D detailed description 85 6.8 digital machine the digital part of the HM301D performs the pr eprocessing and filtering of all the digital signals coming from 4 analog channels. this part has been already described in the biopotential and impedance channel sections. in addition it manages all the device operation related to operating modes, trimming and test procedures, start-up sequence. the digital part can be configured through spi and has a non-volatile memory which carries the trimming words for the analog building blocks. in HM301D the data can be retrieved by two methods: packets streaming mode and read data command mode. these two procedures can be selected by meas_mode bit (set22 <7>). 6.8.1 operating modes the HM301D has the following operating states: sleep, boot, standby, ready, measure, recovery. 6.8.2 sleep this state is active when in any ot her state the rst pin is asserted low 6.8.3 boot this state is reached 100 s after the rst pin is gone to v dd . this function is implemented with an internal counter so to wait the right time for the analog blocks to be stable. the device stays in this state for 600 s before automatically moving to standby. 6.8.4 standby ? packets streaming mode (meas_mode = 0). this state is reachable in two ways: ? from boot state. this means that the boot is correctly performed; ? from measure state, by pulling up the cs pin. this means that the user asks to exit from the measure mode in order to load through spi a new configuration (see spi communication for details). ? read data command mode (meas_mode = 1) table 10. functional modes tm1 tm0 rst pin function description dvss dvss por digital output the rst pin outputs por: high ? device off low ? device on dvss dvdd en digital input the rst pin is configured as enable: high ? power up low ? power down dvdd dvss res - reserved dvdd dvdd res - reserved
detailed description HM301D 30/85 docid026157 rev 4 this state is reachable in two ways ? from boot state. this means that the boot is correctly performed ? from measure state putting the settings_ok_r bit to zero 6.8.5 ready this state is reached from standby mode when the bit settings_ok_r (3dh) is set to 1 and the clock is working correctly. this means that the user has loaded all the configurations and the clock is running correctly. this state is not present when meas_mode = 1. 6.8.6 measure ? packets streaming mode (meas_mode = 0). ? this state is reachable from the in ready st ate putting the cs pin low. when entering the measure state the device automatically in itiates a first fast recovery procedure end then outputs the data on spi ? when in measure state the de vice can pass to stand-by state by pulling the cs pin high. ? read data command mode (meas_mode = 1) ? this state is reachable from standby st ate putting the settings_ok_r bit to 1. when entering the measure state the device automatically initiates a first fast recovery procedure. ? when in measure state the device can pass to stand-by state setting the settings_ok_r bit to 1. figure 12. state machine for packets streaming mode (meas_mode = 0) am17613v1 sleep measure ready boot standby cs pin high
docid026157 rev 4 31/85 HM301D detailed description 85 figure 13. state machine for packets streaming mode (meas_mode = 1) 6.8.7 fast recovery during an overvoltage, overflow condition or at start-up, i.e. a condition where the input voltage is too large or zero, the digital state machine initiate the recovery mode. this procedure is activated when entering the measure state and when an overflow conditions lasts for a longer time than a programmed blanking time. this time is programmable from 2.5 ms to 37.5 ms in 2.5 ms steps by setting the recovery_time_r bits. the recovery procedure can be disabled by setti ng recovery_time_r =1111. in this condition, the digital high pass filters are set by the hcx_ dig_hpf_sel_r (registers 38h and 39h) and not by the hc_dig_ecghpf_sel_r and hc_dig_pmhpf_sel _r. with the recovery mode disabled, it is possible to change the cut off frequency of the analog high pass filters by changing the hc[1- 3]_rhpf_sel_r bits. at the beginning of the recovery mode, the hp f ilters of all the channels, both in the digital as well as in the analog domain, are switched to their highest (5 hz) cut-off frequency, then they are switched to lower frequencies. from 5 hz the cut off is changed to 0.7 hz and then to 0.05 hz. the timing between two different cut-off frequencies is programmable between 0 and 1 s with 200 ms steps (filter_switchtime 1_r / filter_switchtime2_r). so when the maximum time is chosen, the total recovery time is 2 s: 1s for the switching time from 5 hz to 0.7 hz and 1s for the switchi ng time from 0.7 hz to 0.05 hz. the digital hp filter is switched in the same way as the analog hp filter. the only difference is that it stops at the frequency which is selected by the hc_dig_ecghpf_sel_r and hc_dig_pmhpf_sel_r bits. for instance, if the user selects a hp cut-off of 0.7 hz than the filter stops at 0.7 hz. when it is 1 hz the filter switches to 1 hz instead of 0.7 hz. during recovery mode all the ac current injection blocks are disabled, so the signals, hcx_curinj_en and imp_curinj_en are set to 0. am17614v1 sleep measure boot standby settings_ok_r = 1 settings_ok_r = 0
detailed description HM301D 32/85 docid026157 rev 4 6.9 gpio configuration the HM301D has 3 digital gpios. dgio0 and dgio1 are always used as outputs while dgio2 can be configured as input or output by changing the dgio2_config_r bit (address 40h bit #2). each dgio has his own multiplexer that can be configured by changing the corresponding digiox_mus_sel_r<3:0> (registers set25 and set26). the multiplexer configuration is shown in the following tables. table 11. digital gpio output signals (dgio0) register set 26 - address 46 hex - <7:4> dgio0_muxsel_r <3:0> dgio0 0000 pm_rsh 0001 clk_o 0010 pmd1 0011 pmd2 0100 imp_adc_pdm1_o 0101 fchop_o 0110 por_o 0111 not used 1000 ecg_rsh 1001 z_rsh 1010 prefilt_rsh 1011 in_contact_out_flag1 1100 in_contact_out_flag4 1101 in_cck_out1 1110 in_cck_out4 1111 hc1_overfow_flag
docid026157 rev 4 33/85 HM301D detailed description 85 table 12. digital gpio output signals (dgio1) register set 25 - address 45 hex - <3:0> dgio1_muxsel_r <3:0> dgio1 0000 pmd1 0001 hc1_adc_pdm_o 0010 hc2_adc_pdm_o 0011 hc3_adc_pdm_o 0100 imp_adc_pdm2_o 0101 psmon0 0110 not used 0111 ecg_rsh 1000 z_rsh 1001 prefilt_rsh 1010 pm_rsh 1011 in_contact_out_flag2 1100 in_contact_out_flag5 1101 in_cck_out2 1110 in_cck_out5 1111 hc2_overfow_flag
detailed description HM301D 34/85 docid026157 rev 4 description of the signals: ? pm_rsh: ? this signal provides the info rmation about a new data refresh of the lrhb signal path inside the HM301D. this signal must be used to synchronize the mcu readings. in this case the data must be retrieved using the data packet streaming procedure (meas_mode=0). as soon this signal goes hi gh, the mcu can send a train of 80 clock pulses in order to read 64 bits of the data stream. ? ecg_rsh: ? this signal provides the info rmation about a new data refresh of the hrlb signal path inside the HM301D. this signal must be used to synchronize the mcu readings. in this case the data must be retrieved using the normal spi data reading procedure. as soon this signal goes high, the mcu must read directly the ecg_out registers using the word reading procedure as described in figure 15 . to enable the spi data reading the meas_mode bit in set 22 register must be set to 1. ? z_rsh: ? this signal provides the information about a new data refresh of the impedance channel path inside the HM301D. this signal must be used as trigger to synchronize the mcu readings. in this case the data must be retrieved using the normal spi data reading procedure. as soon this signal g oes high, the mcu must read directly the impedance registers using the word reading procedure as described in figure 15 . to enable the spi data reading the meas_mode bit in set 22 register must be set to 1 table 13. digital gpio output signals (dgio2) register set 25 - address 45 hex - <7:4> dgio2_muxsel_r <3:0> dgio2 (dgio2_config_r=1) 0000 pmd2 0001 hc1_overflow_o 0010 hc2_overflow_o 0011 hc3_overflow_o 0100 imp_overflow_o 0101 psmon1 0110 not used 0111 z_rsh 1000 pm_rsh 1001 imp_overfow_flag 1010 ecg_rsh 1011 in_contact_out_flag3 1100 in_contact_out_flag6 1101 in_cck_out3 1110 in_cck_out6 1111 hc3_overfow_flag
docid026157 rev 4 35/85 HM301D detailed description 85 ? prefilt_rsh: ? this signal provides the information about a new data refresh of the pre-filtered signals. this signal must be used to synchr onize the mcu readings . in this case the data must be retrieved using the data packet streaming procedure. as soon this signal goes high, the mcu can send a train of 48 clock pulses in order to read 64 bits of the pre-filtered data stream. ? pmd1, pmd2: ? these signals represent the output of the signal amplit ude detection of the lrhb signal path of the biopotential channels. pmd1 and pmd2 can be configured to provide the data of ch1, ch2 and ch3 according to the pm_sel_r bits (address 28h<6:4>). ? hc1_adc_pdm_o, hc2_adc_ pdm_o, hc3_adc_pdm_o: ? 1bit 2mhz output streams of the adcs of the three acquisition channels; ? hc1_overflow_o, hc1_overflow_o, hc1_overflow_o, imp_overflow_o: ? overflow signals of the three acquisition channels and impedance channel; ? in_contact_out_flag1, in_contact_out_flag2, in_contact_out_flag3, in_contact_out_flag4, in_contact_out_flag5, in_contact_out_flag6: cont act check flags go high if the comparator threshold is crossed. the status of this flags is latched out at the rising edge of internal generated clock. ? in_contact_out1, in_contact_out2, in_contact _out3, in_contact_out4, in_contact_out5, in_contact_out6: outputs of the contact check comparator. these signals are the outputs of the contact check comp arator and give the same information of the in_contact_out_flagx but in asynchronous way. ? hc1_overfow_flag, hc1_overfow_flag, hc1_overfow_flag, imp_overfow_flag: ? hrlb channels and impedance channel overflow flags ? imp_adc_pdm1_o: ? first bit of the ?? stream of the adc of the impedance channel; ? imp_adc_pdm2_o: ? second bit of the ?? stream of the adc of the impedance channel; ? fchop_o: ? chopping signal for the input amplifiers and signal for ac contact check current injection; ? clk_o: ? oscillator output; ? por_o ? power on reset signal. ? psmon0, psmon1 ? power supply voltage monitor (see figure 6.11 ). the dgiox can be also configured as an input. ? to configure dgio0 as input set dgio0_con fig_r bit=0 (set23 digio_io address 40h bit #0). ? to configure dgio1 as input set dgio1_con fig_r bit=0 (set23 digio_io address 40h bit #1). ? to configure dgio2 as input set dgio2_con fig_r bit=0 (set23 digio_io address 40h bit #2). following two tables give an overview of the digital input and output mux configuration
detailed description HM301D 36/85 docid026157 rev 4 ? impinj_ondem_en_i: when low, it disables impedance current injection; ? accc_ondem_en_i: when low, it disables ac contact check current injection by connecting these pins to an mcu io it is po ssible to turn on/off the ac current injection and impedance without interrupting the data stream of the spi port. 6.10 spi interface the HM301D spi port works as a bus slave. the spi allows writ ing and reading the registers of the device. the serial interface works with 4 wires: cs, spc, sdi and sdo. when in measurement mode the spi port works in a particular way where no address is needed for reading the data but the device au tomatically send out the data in a particular output format, see section 6.13 for details. the HM301D spi is capable of being connected in a daisy chain when multiple chips are connected together (see section 6.10.3 ). cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped wh en cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc. all the pins are idle when high. 6.10.1 spi read the read operation is performed by 32 clock pulses. in the first 16 pulses the master sends the read command byte and a dummy byte (ffh) through sdi pin with cs pin low. after that, the muster must put the cs pin high and send the second 16 clock pulses in order to output the read command byte and the data byte through the sdo pin. the read command byte contains the read/write bit (msb) and the register address. table 14. digital gpio input signals digiox_mux_sel[3:0] digio0 digio1 digio2 0000 impinj_ondem_en_i accc_ondem_en_i
docid026157 rev 4 37/85 HM301D detailed description 85 figure 14. single byte reading the figure 15 shows the procedure for a double byte reading. figure 15. double byte reading 6.10.2 spi write the spi write command is performed with 16 cl ock pulses. in the first 8th bit the master sends the read/write command byte; in the second 8th bit the master sends the data byte to write. the command byte contains the read/write bit (msb) and the register address (ad(6:0)). both command byte and data byte must be writt en in msb-first format. table 15. read command bytes write bit (msb) register address 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0
detailed description HM301D 38/85 docid026157 rev 4 figure 16. single byte writing 6.10.3 daisy chain spi in the daisy chain spi configuration, the first slave input (sdi) is connected to the mosi and the first slave output (sdo) is connected to th e second slave input (sdi) and so on. the last slave output is connected to the miso of the master. figure 17. example of daisy chain spi connection with 3 HM301D during the period in which cs stays high, the spi port of each slave is designed to send out during the second group of clock pulses an exac t copy of what it received during the first group of clock pulses. so all the spi ports work as shift registers. when cs is low, all the slaves execute the commands at their respective sdi inputs. table 16. write command byte write bit (msb) register address 0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 spc sdi HM301D sdo slave1 cs spc sdi HM301D sdo slave2 cs spc sdi HM301D sdo slave3 cs
docid026157 rev 4 39/85 HM301D detailed description 85 writing one register needs 16 pulses clock for each device connected in daisy chain. in the below example, three devices are connected in daisy chain so 48 clock pulses are needs to write a register into each of them. during the first 32 cycles the commands are shifted through the chain. in the last 16 bits, cs is pulled low and the devices execute the commands. in this way, each slave can receive its own command. it is also possible to send commands to just the first or the first two slav es by stopping the clock pulses at 16 or 32 respectively and, of course , pulling cs low accordingly. figure 18. example of daisy chain spi writing 1. w: write bit 2. addx<0:6>: register address of the x device of the chain 3. datax<0:7>: data value to be written in the x device of the chain reading in daisy chain needs additional 16 cycles for each device. this is because the devices need the clock to shift the output data through the chain until the data coming from the first slave reaches the master input (miso). the picture below show an example of reading one register (different for each device) with three HM301D connected in chain. am17590v1 16 pulses 16 pulses 16 pulses w - add3 -data3 0xffff 0xffff 0xffff cs spc sdi -1 mosi sdi -2 sdo -1 sdi -3 sdo -2 w - add2 -data2 w -add1 - data1 w -add3 -data3 w -add2 -data2 w - add3 -data3
detailed description HM301D 40/85 docid026157 rev 4 figure 19. example of daisy chain spi reading 1. r: read bit 2. addx<0:6>: register address of the x device of the chain 3. datax<0:7>: data value read in the x device of the chain see 0 for details about reading daisy chain spi when HM301D is in measurement mode. am17591v1 16 pulses 16 pulses 16 pulses r-add3 - 0xff 0xffff 0xffff 0xffff cs spc sdi -1 mosi sdi -2 sdo-1 sdi -3 sdo-2 r-add2 - 0xff r-add1 - 0xff r-add3- 0xff r- add2- 0xff r-add3 - 0xff 0xffff 0xffff sdo-3 miso 16 pulses 16 pulses 16 pulses 0xffff 0xffff 0xffff 0xffff x - add1 - data1 x - add1 - data1 x - add1 - data1 x - add2 - data2 x - add3 - data3 x-add2 - data2 0xffff 0xffff 0xffff
docid026157 rev 4 41/85 HM301D detailed description 85 6.10.4 spi timing figure 20. spi timing 4. values are guaranteed at 10 mhz clock frequency for spi with 4 wires, based on characterization results, not tested in production. 5. measurement points are done at 0.2 iovdd and 0.8 iovdd, for both input and output port. table 17. spi slave timings (iovdd = 1.8 v) symbol parameter test condition min. max. unit t c (spc) spi clock cycle 100 ns f c (spc) spi clock frequency 10 mhz t su (cs) cs setup time 6ns t h (cs) cs hold time 8 t su (si) sdi input setup time 5 t h (si) sdi input hold time 15 t v (so) sdo valid output time 50 t h (so) sdo output hold time 9 t dis (so) sdo output disable time 50 am17592v1 spc cs sdi sdo t su(cs) t v(so) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in
detailed description HM301D 42/85 docid026157 rev 4 6.11 power supply voltage monitor the HM301D is able to monitor the level of analog supply voltage and to give a 2 bits signal named psmon_out. the table below shows the meaning of the psmon_out<1:0>. the psmon_out signal is available for spi readi ng in the out_flag1 register (48h) or in the digio1 and dgio2 with proper co nfiguration of dg io multiplexer. 6.12 registers map table 18. psmon_out signal psmon_out_i<1:0> supply level 00 avdd < 1.62 v 01 1.62 v < avdd < 2.13 v 10 2.13 v < avdd < 3.6 v 11 avdd > 3.6 v table 19. registers map register name register description sub address type set0 enable bits 27h r/w set1 active pacemaker channels, current injection enables 28h r/w set2 avg buffers 29h r/w set3 multi chip configuration, input matrix configuration 2ah r/w set4 input matrix configuration 2bh r/w set5 input matrix configuration 2ch r/w set6 input matrix configuration 2dh r/w set7 input matrix configuration 2eh r/w set8 clock configuration, rld connection 2fh r/w set9 dc contact check settings 30h r/w set10 dc contact check settings 31h r/w set11 dc contact check settings 32h r/w set12 dc contact check comparators settings 33h r/w set13 gain of biopotential channels, ac contact check current injection 34h r/w set14 impedance channel settings 35h r/w set15 gain of impedance channel, lpf and hpf settings of lbhr path 36h r/w
docid026157 rev 4 43/85 HM301D detailed description 85 set16 lpf and hpf settings of hblr path 37h r/w set17 fast startup settings of analog and digital hp filter 38h r/w set18 39h r/w set19 ac current injection phase, rld settings, lpf of impedance channel 3ah r/w set20 recovery time settings, pm detection threshold 3bh r/w set21 pm detection threshold 3ch r/w set22 start output data, hp filter switching time at start-up 3dh r/w set23 digio2 input or output configuration 40h r/w set24 enable psmon, chop, current injection 44h r/w set25 multiplexer configuration for digital gpios digio1 and digio2 45h r/w set26 multiplexer configuration for digital gpio digio0 46h r/w output flags (read only) out_flag0 overflow flags 47h r out_flag1 dc contact check flags 48h r table 19. registers map (continued) register name register description sub address type
detailed description HM301D 44/85 docid026157 rev 4 table 20. registers map register name register description sub address type ecg1_dataout_1 49h r ecg1_dataout_0 4ah r ecg2_dataout_1 4bh r ecg2_dataout_0 4ch r ecg3_dataout_1 4dh r ecg3_dataout_0 4eh r ecg12_dataout_1 4fh r ecg12_dataout_0 50h r ecg23_dataout_1 51h r ecg23_dataout_0 52h r ecg31_dataout_1 53h r ecg31_dataout_0 54h r pm1_dataout_1 55h r pm1_dataout_0 56h r pm2_dataout_1 57h r pm2_dataout_0 58h r impedance_phase_ac_dataout_1 59h r impedance_phase_ac_dataout_0 5ah r impedance_squaring_ac_dataout_1 5bh r impedance_squaring_ac_dataout_0 5ch r impedance_phase_dc_dataout_1 5dh r impedance_phase_dc_dataout_0 5eh r impedance_squaring_dc_dataout_1 5fh r impedance_squaring_dc_dataout_0 60h r contact_check_ dataout_1 61h r contact_check_ dataout_0 62h r
docid026157 rev 4 45/85 HM301D detailed description 85 table 21. data registers (readable only if meas_mode bit is 1) register name register description sub address type ecg1_dataout_1 49h r ecg1_dataout_0 4ah r ecg2_dataout_1 4bh r ecg2_dataout_0 4ch r ecg3_dataout_1 4dh r ecg3_dataout_0 4eh r ecg12_dataout_1 4fh r ecg12_dataout_0 50h r ecg23_dataout_1 51h r ecg23_dataout_0 52h r ecg31_dataout_1 53h r ecg31_dataout_0 54h r pm1_dataout_1 55h r pm1_dataout_0 56h r pm2_dataout_1 57h r pm2_dataout_0 58h r impedance_phase_ac_dataout_1 59h r impedance_phase_ac_dataout_0 5ah r impedance_squaring_ac_dataout_1 5bh r impedance_squaring_ac_dataout_0 5ch r impedance_phase_dc_dataout_1 5dh r impedance_phase_dc_dataout_0 5eh r impedance_squaring_dc_dataout_1 5fh r impedance_squaring_dc_dataout_0 60h r contact_check_ dataout_1 61h r contact_check_ dataout_0 62h r
detailed description HM301D 46/85 docid026157 rev 4 6.12.1 application settings (read/write) table 22. set0 ch_enable (addr 27h) bit name default description 7 sd_en_r 0 enable shield driver 6 wct_en_r 0 enable all wct buffers 5 dig_en_r 0 enable digital filtering of all health channels 4 d2se_en_r 0 enable diff2se buffer of all health channels 3 imp_en_r 0 enable impedance channel 2 hc3_en_r 0 enable health channel 3 1 hc2_en_r 0 enable health channel 2 0 hc1_en_r 0 enable health channel 1 table 23. set1 pm_sel (addr 28h) bit name default descr iption configurations 7 dummy 0 6 pm_sel_r<2> 0 select active lrhb channels: 000 --> lrhb1 data from ch1; lrhb2 off 5 pm_sel_r<1> 0 001 --> lrhb1 data from ch2; lrhb2 off 4 pm_sel_r<0> 0 010 --> lrhb1 data from ch3; lrhb2 off 011 --> lrhb1 data from ch1; lrhb2 data from ch2 100 --> lrhb1 data from ch1; lrhb2 data from ch3 101 --> lrhb1 data from ch2; lrhb2 data from ch3 110 --> lrhb1 off; lrhb2 off 111 --> lrhb1 off; lrhb2 off 3 hc3_curinj_en_r 0 enable health channel 3 current injection 2 hc2_curinj_en_r 0 enable health channel 2 current injection 1 hc1_curinj_en_r 0 enable health channel 1 current injection 0 rld_en_r 0 enable rld driver
docid026157 rev 4 47/85 HM301D detailed description 85 table 24. set 2 avg_ctrl (addr 29h) bit name default description configurations 7 avg_numb_buf_r<3> 0 number of avg buffers used in the system, this determines the compensation capacitance 0000 --> 0 6 avg_numb_buf_r<2> 0 0001 --> 1 5 avg_numb_buf_r<1> 0 0010 --> 2 4 avg_numb_buf_r<0> 0 0011 --> 3 ??? 1111 --> 15 3 avg_en_buf4_r 0 enable avg buffer 4 2 avg_en_buf3_r 0 enable avg buffer 3 1 avg_en_buf2_r 0 enable avg buffer 2 0 avg_en_buf1_r 0 enable avg buffer 1 table 25. set3 incon_hcsel_1 (2ah) bit name default description configurations 7 ndev_bit1 0 number of devices in application: 00 --> 1 device 6 ndev_bit0 0 01 --> 2 devices 10 --> 3 devices 11 --> 4 devices 5 inputcon_in1n_hcsel_r<2> 1 connect input pad in1n to one of the 6 health channel inputs 000 --> ch1 positive 4 inputcon_in1n_hcsel_r<1> 1 001 --> ch1 negative 3 inputcon_in1n_hcsel_r<0> 1 010 --> ch2 positive 011 --> ch2 negative 100 --> ch3 positive 101 --> ch3 negative 110 --> unconnected 111 --> unconnected 2 inputcon_in1p_hcsel_r<2> 1 connect input pad in1p to one of the 6 channel inputs same setting of inputcon_in1n_hcsel_r 1 inputcon_in1p_hcsel_r<1> 1 0 inputcon_in1p_hcsel_r<0> 1
detailed description HM301D 48/85 docid026157 rev 4 table 26. set4 incon_hcsel_2 (2bh) bit name default description configurations 7dummy 0 6dummy 0 5 inputcon_in2n_hcsel_r<2> 1 connect input pad in2n to one of the 6 health channel inputs same setting of inputcon_in1n_hcsel_r 4 inputcon_in2n_hcsel_r<1> 1 3 inputcon_in2n_hcsel_r<0> 1 2 inputcon_in2p_hcsel_r<2> 1 connect input pad in2p to one of the 6 health channel inputs same setting of inputcon_in1n_hcsel_r 1 inputcon_in2p_hcsel_r<1> 1 0 inputcon_in2p_hcsel_r<0> 1 table 27. set5 incon_hcsel_3 (2ch) bit name default description configurations 7dummy 0 6dummy 0 5 inputcon_in3n_hcsel_r<2> 1 connect input pad in3n to one of the 6 health channel inputs same setting of inputcon_in1n_hcsel_r 4 inputcon_in3n_hcsel_r<1> 1 3 inputcon_in3n_hcsel_r<0> 1 2 inputcon_in3p_hcsel_r<2> 1 connect input pad in3p to one of the 6 health channel inputs same setting of inputcon_in1n_hcsel_r 1 inputcon_in3p_hcsel_r<1> 1 0 inputcon_in3p_hcsel_r<0> 1 table 28. set6 incon_avg_1 (2dh) bit name default description configurations 7dummy 0 6dummy 0 5 inputcon_avg2_r<2> 1 connect input avg buffer2 to any of the 6 input pads inxy (x=1,2,3 y=p/n) 000 --> in1p 4 inputcon_avg2_r<1> 1 001 --> in1n 3 inputcon_avg2_r<0> 1 010 --> in2p 011 --> in2n 100 --> in3p 101 --> in3n 110 --> unconnected 111 --> unconnected 2 inputcon_avg1_r<2> 1 connect input avg buffer1 to any of the 6 input pads inxy (x=1,2,3 y=p/n) same setting of inputcon_avg2_r 1 inputcon_avg1_r<1> 1 0 inputcon_avg1_r<0> 1
docid026157 rev 4 49/85 HM301D detailed description 85 table 29. set7 incon_avg_2 (2eh) bit name default description configurations 7dummy 0 6dummy 0 5 inputcon_avg4_r<2> 1 connect input avg buffer4 to any of the 6 input pads inxy (x=1,2,3 y=p/n) same setting of inputcon_avg2_r 4 inputcon_avg4_r<1> 1 3 inputcon_avg4_r<0> 1 2 inputcon_avg3_r<2> 1 connect input avg buffer3 to any of the 6 input pads inxy (x=1,2,3 y=p/n) same setting of inputcon_avg2_r 1 inputcon_avg3_r<1> 1 0 inputcon_avg3_r<0> 1 table 30. set8 incon_rld (2fh) bit name default description configurations 7dummy 0 6 ckext_en 0 enable clock output 0: no clock out on ckext pin 1: clock out on ckext pin 5 clk_sel_r<1> 0 select the internal, external or xtal oscillator 00 --> ring oscillator 4 clk_sel_r<0> 0 01 --> xtal oscillator 10 --> external clock 3 psmon_sel_r 1 change the common mode voltage of ina. 0-> vref=0.7v to use when supply voltage is lower than 2v, typical 1.8v 1-> vref=1,0v to use when supply voltage is higher than 2v, typical 3.3v. 2 inputcon_rld_sel_r<2> 1 connect the rld output to any of the inputs pads inxn/p, for x=1,2,3 000 --> in1p 1 inputcon_rld_sel_r<1> 1 001 --> in1n 0 inputcon_rld_sel_r<0> 1 010 --> in2p 011 --> in2n 100 --> in3p 101 --> in3n 110 --> unconnected 111 --> unconnected
detailed description HM301D 50/85 docid026157 rev 4 table 31. set9 cck_en_1 (30h) bit name default description configurations 7 in2n_contact_pdn_r 0 contact check enable signal for n-side of dc contact check connected to in in2n 0: current off 1: current on 6 in2n_contact_pdp_r 0 contact check enable signal for p-side of dc contact check connected to in2n same as in2n_contact_en_r 5 in2p_contact_pdn_r 0 contact check enable signal for n-side of dc contact check connected to in2p 4 in2p_contact_pdp_r 0 contact check enable signal for p-side of dc contact check connected to in2p 3 in1n_contact_pdn_r 0 contact check enable signal for n-side of dc contact check connected to in1n 2 in1n_contact_pdp_r 0 contact check enable signal for p-side of dc contact check connected to in1n 1 in1p_contact_pdn_r 0 contact check enable signal for n-side of dc contact check connected to in1p 0 in1p_contact_pdp_r 0 contact check enable signal for p-side of dc contact check connected to in1p table 32. set10 cck_en_2 (31h) bit name default description configurations 7 in1n_cont_cur_r<1> 0 select the current (25/50/100/200na) of the contact check connected to in1n 00 --> 25 na 6 in1n_cont_cur_r<0> 0 01 --> 50 na 10 --> 100 na 11 --> 200 na 5 in1p_cont_cur_r<1> 0 select the current (25/50/100/200na) of the contact check connected to in1p same setting of in1n_cont_cur_r 4 in1p_cont_cur_r<0> 0 3 in3n_contact_pdn_r 0 contact check enable signal for n-side of dc contact check connected to in3n 2 in3n_contact_pdp_r 0 contact check enable signal for p-side of dc contact check connected to in3n 1 in3p_contact_pdn_r 0 contact check enable signal for n-side of dc contact check connected to in3p 0 in3p_contact_pdp_r 0 contact check enable signal for p-side of dc contact check connected to in3p
docid026157 rev 4 51/85 HM301D detailed description 85 table 33. set11 cck_cur (32h) bit name default description configurations 7 in3n_cont_cur_r<1> 0 select the current (25/50/100/200na) of the contact check connected to in3n same setting of in1n_cont_cur_r 6 in3n_cont_cur_r<0> 0 5 in3p_cont_cur_r<1> 0 select the current (25/50/100/200na) of the contact check connected to in3p same setting of in1n_cont_cur_r 4 in3p_cont_cur_r<0> 0 3 in2n_cont_cur_r<1> 0 select the current (25/50/100/200na) of the contact check connected to in2n same setting of in1n_cont_cur_r 2 in2n_cont_cur_r<0> 0 1 in2p_cont_cur_r<1> 0 select the current (25/50/100/200na) of the contact check connected to in2p same setting of in1n_cont_cur_r 0 in2p_cont_cur_r<0> 0
detailed description HM301D 52/85 docid026157 rev 4 table 34. set12 cck_trsh (33h) bit name default description configurations 7 cck_threshp_sel_r<3> 0 select threshold at the vdd side for the dc contact at all inputs (typical values) 0000 --> vdd-60uv 6 cck_threshp_sel_r<2> 0 0001 --> vdd-102mv 5 cck_threshp_sel_r<1> 0 0010 --> vdd-204 mv 4 cck_threshp_sel_r<0> 0 0011 --> vdd-306mv 0100 --> vdd-408 mv 0101 --> vdd-510mv 0110 --> vdd-612mv 0111 --> vdd-714mv 1000 --> vdd-816mv 1001 --> vdd-918mv 1010 --> vdd-1.020 v 1011 --> vdd- 1.122 v 1100 --> vdd-1.224 v 1101 --> vdd-1.326 v 1110 --> vdd-1.427 v 1111 --> vdd-1.529 v 3 cck_threshn_sel_r<3> 0 select threshold at the v ss side for the dc contact at all inputs (typical values) 0000 --> 60uv 2 cck_threshn_sel_r<2> 0 0001 --> 102mv 1 cck_threshn_sel_r<1> 0 0010 --> 204 mv 0 cck_threshn_sel_r<0> 0 0011 --> 306mv 0100 --> 408 mv 0101 --> 510mv 0110 --> 612mv 0111 --> 714mv 1000 --> 816mv 1001 --> 918mv 1010 --> 1.020 v 1011 --> 1.122 v 1100 --> 1.224 v 1101 --> 1.326 v 1110 --> 1. 427 v
docid026157 rev 4 53/85 HM301D detailed description 85 table 35. set13 hc_ana_ctrl (34h) bit name default description configurations 7 dataout_prefilter_en 0 enabl e for data out pre-filter 6 hc_pga_gain_r<1> 1 select the gain of the pga (1, 2, 4) for all health channels 00 --> 4 5 hc_pga_gain_r<0> 1 01 --> 2 10 --> 4/3 11 --> 1 4 hc_ina_gain_r<1> 0 select the gain of the ina (8 or 16) for all health channels 00 --> 8 3 hc_ina_gain_r<0> 0 01 --> 8 10 --> 16 11 --> 16 2 hc_curinj_freq_r 0 select the current injection frequency (2,5khz or 5khz) for all health channels 0 --> 2.5 khz 1 --> 5 khz 1 hc_curinj_cur_r<1> 0 select the current injection (5ua, 10ua or 20ua) all health channels 00 --> 5 a 0 hc_curinj_cur_r<0> 0 01 --> 10 a 10 --> 20 a table 36. set14 imp_ana_ctrl (35h) bit name default description configurations 7dummy 0 6 imp_ina_gain_r<1> 0 select the gain of the ina (8 or 16) for the impedance channel 00 --> 8 5 imp_ina_gain_r<0> 0 01 --> 8 10 --> 16 11 --> 16 4 imp_curinj_cur_r<1> 0 select the current injection (5 a, 10 a or 20 a) impedance channel 00 --> 5 a 3 imp_curinj_cur_r<0> 0 01 --> 10 a 10 --> 20 a 2 imp_curinj_freq_r<2> 0 select the current injection frequency. this is equal to the chopping frequency 000 --> fchop = 20 khz 1 imp_curinj_freq_r<1> 0 001 --> fchop = 25 khz 0 imp_curinj_freq_r<0> 0 010 --> fchop = 31.25 khz 011 --> fchop = 35.714 khz 100 --> fchop = 41.667 khz 101 --> fchop = 45.455 khz 110 --> fchop = 50 khz
detailed description HM301D 54/85 docid026157 rev 4 table 37. set15 ecg_digfilt_ctrl (36h) bit name default description configurations 7 hc_dig_ecghpf_sel_r<2> 1 digital hpf cut-off frequency selection for the hrlb signal of all health channels. these settings are active when the recovery mode is on. 000 --> 5 hz 6 hc_dig_ecghpf_sel_r<1> 1 001 --> 2 hz 5 hc_dig_ecghpf_sel_r<0> 0 010 --> 1 hz 011 --> 0.7 hz 100 --> 0.5 hz 101 --> 0.1 hz 110--> 0.05 hz 4 hc_dig_ecglpf_sel_r<3> 0 digital lpf cut-off frequency selection for the hrlb signal of all health channels. 1000 --> 600 hz 3 hc_dig_ecglpf_sel_r<2> 0 0000 --> 300 hz 2 hc_dig_ecglpf_sel_r<1> 0 0001 --> 200 hz 1 hc_dig_ecglpf_sel_r<0> 0 0010 --> 150 hz 0011 --> 100 hz 0100 --> 75 hz 0101 --> 50 hz 0110 --> 37.5 hz 0111 --> 25 hz 0dummy 0 table 38. set16 pm_digfilt_ctrl (37h) bit name default description configurations 7dummy 0 6 imp_pga_gain_r<1> 0 select the gain of the pga (1, 2, 4) for the impedance channel 00 --> 4 01 --> 2 5 imp_pga_gain_r<0> 0 10 --> 4/3 11 --> 1 4dummy 0 3 hc_dig_pmhpf_sel_r<2> 0 digital hpf cut-off frequency selection for the lrhb signal of all health channels. these settings are active when the recovery mode is on. 000 --> 5 hz 2 hc_dig_pmhpf_sel_r<1> 1 001 --> 1 hz 1 hc_dig_pmhpf_sel_r<0> 1 010 --> 0.7 hz 011 --> 0.05 hz 100 --> 1 khz 0 hc_dig_pmlpf_sel_r 0 digital lpf cut-off frequency selection for the lrhb signal of all health channels. 0 --> 10 khz 1 --> 5 khz
docid026157 rev 4 55/85 HM301D detailed description 85 table 39. set17 hc_digfilt_ctrl (38h) bit name default description configurations 7 hc3_dig_hpf_sel_r<2> 0 digital hp cut off frequency for health channel 3. these settings are active when the recovery mode is off 000 --> hrlb = 5hz; lrhb = 5hz 6 hc3_dig_hpf_sel_r<1> 0 001 --> hrlb = 2hz; lrhb = 1hz 5 hc3_dig_hpf_sel_r<0> 0 010 --> hrlb = 1hz; lrhb = 1hz 011 --> hrlb = 0.7hz; lrhb = 0.7hz 100 --> hrlb = 0.5hz; lrhb = 0.7hz 101 --> hrlb = 0.1hz; lrhb = 0.05hz 110 --> hrlb = 0.05hz; lrhb = 0.05hz 4 hc2_dig_hpf_sel_r<2> 0 digital hp cut off frequency for health channel 2. these settings are active when the recovery mode is off same setting of hc3_dig_hpf_sel_r 3 hc2_dig_hpf_sel_r<1> 0 2 hc2_dig_hpf_sel_r<0> 0 1 hc1_dig_hpf_sel_r<2> 0 digital hp cut off frequency for health channel 1. these settings are active when the recovery mode is off same setting of hc3_dig_hpf_sel_r 0 hc1_dig_hpf_sel_r<1> 0 table 40. set18 hc_hpfana_ctrl (39h) bit name default description configurations 7 hc1_dig_hpf_sel_r<0> 0 6dummy 0 5 hc3_rhpf_sel_r<1> 0 select cut- off frequency of analog filter connected to hc3. these settings are active when the recovery mode is off. when recovery mode is on they are set at 0.05hz. 00 --> 5hz 4 hc3_rhpf_sel_r<0> 0 01 --> 0.7hz 10 --> 0.05hz 11 --> 0.05hz 3 hc2_rhpf_sel_r<1> 0 select cut- off frequency of analog filter connected to hc2. these settings are active when the recovery mode is off. when recovery mode is on they are set at 0.05hz. same setting of hc3_rhpf_sel_r 2 hc2_rhpf_sel_r<0> 0 1 hc1_rhpf_sel_r<1> 0 select cut- off frequency of analog filter connected to hc1. these settings are active when the recovery mode is off. when recovery mode is on they are set at 0.05hz. same setting of hc3_rhpf_sel_r 0 hc1_rhpf_sel_r<0> 0
detailed description HM301D 56/85 docid026157 rev 4 table 41. set19 rld_ctrl (3ah) bit name default description configurations 7 hc3_phaserev_r 0 reverse the phase of the injection frequency of health channel 3. used in unipolar measurements. 6 hc2_phaserev_r 0 reverse the phase of the injection frequency of health channel 2. used in unipolar measurements. 5 hc1_phaserev_r 0 reverse the phase of the injection frequency of health channel 1. used in unipolar measurements. 4 rld_ref_sel_r<1> 0 select reference for rld 00 --> 0.7 v 3 rld_ref_sel_r<0> 0 01 --> 1 v 10 --> 1.49 v 2 vref_sel_r 0 register to select internal or external reference. 0->external reference; 1-> internal reference 1 rld_cut_r 0 register to cut or close rld loop 0 --> closed 1 --> open 0 imp_dig_lpf_sel_r 0 digital lpf cut-off frequency selection for impedance channel 0 --> 20 hz 1 --> 1 hz
docid026157 rev 4 57/85 HM301D detailed description 85 table 42. set20 recovery_time (3bh) bit name default description configurations 7dummy 0 6dummy 0 5dummy 0 4 recovery_time_r<3> 0 select the blanking time for overflow detection in steps of 2,5 ms. from 2,5 till 37,5ms. can be put off as well. 0000 --> 2.5 ms 3 recovery_time_r<2> 0 0001 --> 5 ms 2 recovery_time_r<1> 0 0010 --> 7.5 ms 1 recovery_time_r<0> 0 0011 --> 10 ms 0100 --> 12.5 ms 0101 --> 15 ms 0110 --> 17.5 ms 0111 --> 20 ms 1000 --> 22.5 ms 1001 --> 25 ms 1010 --> 27.5 ms 1011 --> 30 ms 1100 --> 32.5 ms 1101 --> 35 ms 1110 --> 37.5 ms 1111 --> recovery mode off 0 hc_pmd_thres_r<8> 0 pacemaker detection threshold table 43. set21 pmd_trsh (3ch) bit name default description configurations 7 hc_pmd_thres_r<7> 0 pacemaker detection threshold 6 hc_pmd_thres_r<6> 0 5 hc_pmd_thres_r<5> 0 4 hc_pmd_thres_r<4> 0 3 hc_pmd_thres_r<3> 0 2 hc_pmd_thres_r<2> 0 1 hc_pmd_thres_r<1> 0 0 hc_pmd_thres_r<0> 0
detailed description HM301D 58/85 docid026157 rev 4 table 44. set22 filter_swtime (3dh) bit name default description configurations 7 meas_mode 0 measurement mode selection 0-> packets streaming 1-> read data command 6 settings_ok_r 0 starts measurement mode 5 filter_switchtime2_r<2> 0 select the switching time for the 2nd cut-off frequency step 0,7hz-0,05hz 000 --> 200 ms 4 filter_switchtime2_r<1> 0 001 --> 400 ms 3 filter_switchtime2_r<0> 0 010 --> 600 ms 011 --> 800 ms 100 to 111 --> 1 s 2 filter_switchtime1_r<2> 0 select the switching time for the first cut-off frequency step 5hz-0,7hz same setting of filter_switchtime2_r 1 filter_switchtime1_r<1> 0 0 filter_switchtime1_r<0> 0 table 45. set23 digio_io (40h) bit name default description 7dummy 0 6dummy 0 5dummy 0 4dummy 0 3dummy 0 2 digio2_config_r 1 to configure digiox in input or output mode 0: input; 1: output 1 digio1_config_r 1 0 digio0_config_r 1 table 46. set24 imp_cur_en (44h) bit name default description 7dummy 0 6 imp_curinj_en_r 1 enable impedance current injection (cip, cin current generators) 5 reserved 0 4 reserved 0 3 reserved 0 2 reserved 0 1 reserved 0 0 reserved 0
docid026157 rev 4 59/85 HM301D detailed description 85 table 47. set25 digio12_sel (45h) bit name default description 7 digio2_muxsel_r<3> 0 select input signal for digio2 6 digio2_muxsel_r<2> 0 5 digio2_muxsel_r<1> 0 4 digio2_muxsel_r<0> 0 3 digio1_muxsel_r<3> 0 select input signal for digio1 2 digio1_muxsel_r<2> 0 1 digio1_muxsel_r<1> 0 0 digio1_muxsel_r<0> 0 table 48. set26 digio0_sel (46h) bit name default description 7 digio0_muxsel_r<3> 0 select input signal for digio0 6 digio0_muxsel_r<2> 0 5 digio0_muxsel_r<1> 0 4 digio0_muxsel_r<0> 0 3dummy 0 2dummy 0 1dummy 0 0dummy 0
detailed description HM301D 60/85 docid026157 rev 4 6.12.2 output flags (read only) table 49. out_flag0 (47h) bit name def. description 7 dummy 6 imp_overflow_r 0 impedance channel is in overflow mode 5 hc3_overflow_r 0 channel 3 is in overflow mode 4 hc2_overflow_r 0 channel 2 is in overflow mode 3 hc1_overflow_r 0 channel 1 is in overflow mode 2 dummy 0 1 dummy 0 0 dummy 0 table 50. out_flag1 (48h) bit name def. description 7 psmon_out_r<1> 0 6 psmon_out_r<0> 0 5 in3n_contact_out_r 0 in3n has bad contact. this is an or of in3n_contact_outp_i & in3n_contact_outn_i 4 in3p_contact_out_r 0 in3p has bad contact. this is an or of in3p_contact_outp_i & in3p_contact_outn_i 3 in2n_contact_out_r 0 in2n has bad contact. this is an or of in2n_contact_outp_i & in2n_contact_outn_i 2 in2p_contact_out_r 0 in2p has bad contact. this is an or of in2p_contact_outp_i & in2p_contact_outn_i 1 in1n_contact_out_r 0 in1n has bad contact. this is an or of in1n_contact_outp_i & in1n_contact_outn_i 0 in1_contact_out_r 0 in1p has bad contact. this is an or of in1p_contact_outp_i & in1p_contact_outn_i
docid026157 rev 4 61/85 HM301D detailed description 85 6.12.3 data registers (readab le only if meas_mode = 1) table 51. ecg1_dataout_1 (49h) bit name def. description 7 ecg1_dataout_r<15> 0 msb of hrlb channel 1. this regist er contains the most significant byte of the output data from th e hrlb1 channel and it is readable when meas_mode=1 6 ecg1_dataout_r<14> 0 5 ecg1_dataout_r<13> 0 4 ecg1_dataout_r<12> 0 3 ecg1_dataout_r<11> 0 2 ecg1_dataout_r<10> 0 1 ecg1_dataout_r<9> 0 0 ecg1_dataout_r<8> 0 table 52. cg1_dataout_0 (4ah) bit name def. description 7 ecg1_dataout_r<7> 0 lsb of hrlb channel 1. this register contains the least significant byte of the output data from th e hrlb1 channel and it is readable when meas_mode=1 6 ecg1_dataout_r<6> 0 5 ecg1_dataout_r<5> 0 4 ecg1_dataout_r<4> 0 3 ecg1_dataout_r<3> 0 2 ecg1_dataout_r<2> 0 1 ecg1_dataout_r<1> 0 0 ecg1_dataout_r<0> 0 table 53. ecg2_dataout_1 (4bh) bit name def. description 7 ecg2_dataout_r<15> 0 msb of hrlb channel 2. this regist er contains the most significant byte of the output data from th e hrlb2 channel and it is readable when meas_mode=1 6 ecg2_dataout_r<14> 0 5 ecg2_dataout_r<13> 0 4 ecg2_dataout_r<12> 0 3 ecg2_dataout_r<11> 0 2 ecg2_dataout_r<10> 0 1 ecg2_dataout_r<9> 0 0 ecg2_dataout_r<8> 0
detailed description HM301D 62/85 docid026157 rev 4 table 54. ecg2_dataout_0 (4ch) bit name def. description 7 ecg2_dataout_r<7> 0 lsb of hrlb channel 2. this register contains the least significant byte of the output data from th e hrlb2 channel and it is readable when meas_mode=1 6 ecg2_dataout_r<6> 0 5 ecg2_dataout_r<5> 0 4 ecg2_dataout_r<4> 0 3 ecg2_dataout_r<3> 0 2 ecg2_dataout_r<2> 0 1 ecg2_dataout_r<1> 0 0 ecg2_dataout_r<0> 0 table 55. ecg3_dataout_1 (4dh) bit name def. description 7 ecg3_dataout_r<15> 0 msb of hrlb channel 3. this regist er contains the most significant byte of the output data from th e hrlb3 channel and it is readable when meas_mode=1 6 ecg3_dataout_r<14> 0 5 ecg3_dataout_r<13> 0 4 ecg3_dataout_r<12> 0 3 ecg3_dataout_r<11> 0 2 ecg3_dataout_r<10> 0 1 ecg3_dataout_r<9> 0 0 ecg3_dataout_r<8> 0 table 56. ecg3_dataout_0 (4eh) bit name def. description 7 ecg3_dataout_r<7> 0 lsb of hrlb channel 3. this register contains the least significant byte of the output data from th e hrlb3 channel and it is readable when meas_mode=1 6 ecg3_dataout_r<6> 0 5 ecg3_dataout_r<5> 0 4 ecg3_dataout_r<4> 0 3 ecg3_dataout_r<3> 0 2 ecg3_dataout_r<2> 0 1 ecg3_dataout_r<1> 0 0 ecg3_dataout_r<0> 0
docid026157 rev 4 63/85 HM301D detailed description 85 table 57. ecg12_dataout_1 (4fh) bit name def. description 7 ecg12_dataout_r<15> 0 msb of ecg12_dataout. this register contains the most significant byte of the half sum between the output data from the ecg1 chain and the output data from the ecg2 chain and it is readable when meas_mode=1 6 ecg12_dataout_r<14> 0 5 ecg12_dataout_r<13> 0 4 ecg12_dataout_r<12> 0 3 ecg12_dataout_r<11> 0 2 ecg12_dataout_r<10> 0 1 ecg12_dataout_r<9> 0 0 ecg12_dataout_r<8> 0 table 58. ecg12_dataout_0 (50h) bit name def. description 7 ecg12_dataout_r<7> 0 lsb of ecg12_dataout. this register contains the least significant byte of the half sum between the output data from the ecg1 chain and the output data from the ecg2 chain and it is readable when meas_mode=1 6 ecg12_dataout_r<6> 0 5 ecg12_dataout_r<5> 0 4 ecg12_dataout_r<4> 0 3 ecg12_dataout_r<3> 0 2 ecg12_dataout_r<2> 0 1 ecg12_dataout_r<1> 0 0 ecg12_dataout_r<0> 0 table 59. ecg23_dataout_1 (51h) bit name def. description 7 ecg23_dataout_r<15> 0 msb of ecg23_dataout. this register contains the most significant byte of the half sum between the output data from the ecg2 chain and the output data from the ecg3 chain and it is readable when meas_mode=1 6 ecg23_dataout_r<14> 0 5 ecg23_dataout_r<13> 0 4 ecg23_dataout_r<12> 0 3 ecg23_dataout_r<11> 0 2 ecg23_dataout_r<10> 0 1 ecg23_dataout_r<9> 0 0 ecg23_dataout_r<8> 0
detailed description HM301D 64/85 docid026157 rev 4 table 60. ecg23_dataout_0 (52h) bit name def. description 7 ecg23_dataout_r<7> 0 lsb of ecg23_dataout. this register contains the least significant byte of the half sum between the output data from the ecg2 chain and the output data from the ecg3 chain and it is readable when meas_mode=1 6 ecg23_dataout_r<6> 0 5 ecg23_dataout_r<5> 0 4 ecg23_dataout_r<4> 0 3 ecg23_dataout_r<3> 0 2 ecg23_dataout_r<2> 0 1 ecg23_dataout_r<1> 0 0 ecg23_dataout_r<0> 0 table 61. ecg31_dataout_1 (53h) bit name def. description 7 ecg31_dataout_r<15> 0 msb of ecg31_dataout. this register contains the most significant byte of the half sum between the output data from the ecg3 chain and the output data from the ecg1 chain and it is readable when meas_mode=1 6 ecg31_dataout_r<14> 0 5 ecg31_dataout_r<13> 0 4 ecg31_dataout_r<12> 0 3 ecg31_dataout_r<11> 0 2 ecg31_dataout_r<10> 0 1 ecg31_dataout_r<9> 0 0 ecg31_dataout_r<8> 0 table 62. ecg31_dataout_0 (54h) bit name def. description 7 ecg31_dataout_r<7> 0 l sb of ecg31_dataout. this register contains the least significant byte of the half sum between the output data from the ecg3 chain and the output data from the ecg1 chain and it is readable when meas_mode=1 6 ecg31_dataout_r<6> 0 5 ecg31_dataout_r<5> 0 4 ecg31_dataout_r<4> 0 3 ecg31_dataout_r<3> 0 2 ecg31_dataout_r<2> 0 1 ecg31_dataout_r<1> 0 0 ecg31_dataout_r<0> 0
docid026157 rev 4 65/85 HM301D detailed description 85 table 63. pm1_dataout_1 (55h) bit name def. description 7 pm1_dataout_r<15> 0 msb of lrhb channel 1. this regist er contains the most significant byte of the output data from the lrhb 1 channel and it is readable when meas_mode=1 6 pm1_dataout_r<14> 0 5 pm1_dataout_r<13> 0 4 pm1_dataout_r<12> 0 3 pm1_dataout_r<11> 0 2 pm1_dataout_r<10> 0 1 pm1_dataout_r<9> 0 0 pm1_dataout_r<8> 0 table 64. pm1_dataout_0 (56h) bit name def. description 7 pm1_dataout_r<7> 0 lsb of lrhb channel 1. this register contains the least significant byte of the output data from th e lrhb1 channel and it is readable when meas_mode=1 6 pm1_dataout_r<6> 0 5 pm1_dataout_r<5> 0 4 pm1_dataout_r<4> 0 3 pm1_dataout_r<3> 0 2 pm1_dataout_r<2> 0 1 pm1_dataout_r<1> 0 0 pm1_dataout_r<0> 0 table 65. pm2_dataout_1 (57h) bit name def. description 7 pm2_dataout_r<15> 0 msb of lrhb channel 2. this regist er contains the most significant byte of the output data from th e lrhb2 channel and it is readable when meas_mode=1 6 pm2_dataout_r<14> 0 5 pm2_dataout_r<13> 0 4 pm2_dataout_r<12> 0 3 pm2_dataout_r<11> 0 2 pm2_dataout_r<10> 0 1 pm2_dataout_r<9> 0 0 pm2_dataout_r<8> 0
detailed description HM301D 66/85 docid026157 rev 4 table 66. pm2_dataout_0 (58h) bit name def. description 7 pm2_dataout_r<7> 0 lsb of lrhb channel 2. this register contains the least significant byte of the output data from th e lrhb2 channel and it is readable when meas_mode=1 6 pm2_dataout_r<6> 0 5 pm2_dataout_r<5> 0 4 pm2_dataout_r<4> 0 3 pm2_dataout_r<3> 0 2 pm2_dataout_r<2> 0 1 pm2_dataout_r<1> 0 0 pm2_dataout_r<0> 0 table 67. impedance_phas e_ac_dataout_1 (59h) bit name def. description 7 impp_ac_dataout_r<15> 0 msb of impp_ac_dataout. this register contains the most significant byte of the output data from the impedance phase ac and it is readable when meas_mode=1 6 impp_ac_dataout_r<14> 0 5 impp_ac_dataout_r<13> 0 4 impp_ac_dataout_r<12> 0 3 impp_ac_dataout_r<11> 0 2 impp_ac_dataout_r<10> 0 1 impp_ac_dataout_r<9> 0 0 impp_ac_dataout_r<8> 0 table 68. impedance_phase_ac_dataout_0 (5ah) bit name def. description 7 impp_ac_dataout_r<7> 0 lsb of impp_ac_dataout. this register contains the least significant byte of the output data from the impedance phase ac and it is readable when meas_mode=1 6 impp_ac_dataout_r<6> 0 5 impp_ac_dataout_r<5> 0 4 impp_ac_dataout_r<4> 0 3 impp_ac_dataout_r<3> 0 2 impp_ac_dataout_r<2> 0 1 impp_ac_dataout_r<1> 0 0 impp_ac_dataout_r<0> 0
docid026157 rev 4 67/85 HM301D detailed description 85 table 69. impedance_squaring_ac_dataout_1 (5bh) bit name def. description 7 impq_ac_dataout_r<15> 0 msb of impq_ac_dataout. this register contains the most significant byte of the output data from the impedance squaring ac and it is readable when meas_mode=1 6 impq _ac_dataout_r<14> 0 5 impq _ac_dataout_r<13> 0 4 impq _ac_dataout_r<12> 0 3 impq _ac_dataout_r<11> 0 2 impq _ac_dataout_r<10> 0 1 impq _ac_dataout_r<9> 0 0 impq _ac_dataout_r<8> 0 table 70. impedance_squaring_ac_dataout_0 (5ch) bit name def. description 7 impq _ac_dataout_r<7> 0 lsb of impp_ac_dataout. this register contains the least significant byte of the output data from the impedance squaring ac and it is readable when meas_mode=1 6 impq _ac_dataout_r<6> 0 5 impq _ac_dataout_r<5> 0 4 impq _ac_dataout_r<4> 0 3 impq _ac_dataout_r<3> 0 2 impq _ac_dataout_r<2> 0 1 impq _ac_dataout_r<1> 0 0 impq _ac_dataout_r<0> 0 table 71. impedance_phase_dc_dataout_1 (5dh) bit name def. description 7 impp_dc_dataout_r<15> 0 msb of impp_dc_dataout. this register contains the most significant byte of the output data from the impedance phase dc and it is readable when meas_mode=1 6 impp_dc_dataout_r<14> 0 5 impp_dc_dataout_r<13> 0 4 impp_dc_dataout_r<12> 0 3 impp_dc_dataout_r<11> 0 2 impp_dc_dataout_r<10> 0 1 impp_dc_dataout_r<9> 0 0 impp_dc_dataout_r<8> 0
detailed description HM301D 68/85 docid026157 rev 4 table 72. impedance_pha se_dc_dataout_0 (5eh) bit name def. description 7 impp_dc_dataout_r<7> 0 lsb of impp_dc_dataout. this register contains the least significant byte of the output data from the impedance phase dc and it is readable when meas_mode=1 6 impp_dc_dataout_r<6> 0 5 impp_dc_dataout_r<5> 0 4 impp_dc_dataout_r<4> 0 3 impp_dc_dataout_r<3> 0 2 impp_dc_dataout_r<2> 0 1 impp_dc_dataout_r<1> 0 0 impp_dc_dataout_r<0> 0 table 73. impedance_squaring_dc_dataout_1 (5fh) bit name def. description 7 impq_dc_dataout_r<15> 0 msb of impq_dc_dataout. this register contains the most significant byte of the output data from the impedance squaring dc and it is readable when meas_mode=1 6 impq _dc_dataout_r<14> 0 5 impq _dc_dataout_r<13> 0 4 impq _dc_dataout_r<12> 0 3 impq _dc_dataout_r<11> 0 2 impq _dc_dataout_r<10> 0 1 impq _dc_dataout_r<9> 0 0 impq _dc_dataout_r<8> 0 table 74. impedance_squari ng_dc_dataout_0 (60h) bit name def. description 7 impq _dc_dataout_r<7> 0 lsb of impp_dc_dataout. this register contains the least significant byte of the output data from the impedance squaring dc and it is readable when meas_mode=1 6 impq _dc_dataout_r<6> 0 5 impq _dc_dataout_r<5> 0 4 impq _dc_dataout_r<4> 0 3 impq _dc_dataout_r<3> 0 2 impq _dc_dataout_r<2> 0 1 impq _dc_dataout_r<1> 0 0 impq _dc_dataout_r<0> 0
docid026157 rev 4 69/85 HM301D detailed description 85 6.13 output data format in order to optimize the communication betwee n the HM301D and the microcontroller, the HM301D implements an automatic data transm ission able to minimize the communication load. in order to read the device data, the mcu doesn't need to send the register addresses to the device but it is the HM301D which c ontinuously sends the data to the mcu. these data are organized in a packet which presents an added header in order to describe the meaning of the data included inside the packet. anyhow the mcu can stop the data flow by pulling up the cs pin anytime. all the data values are in binary twos complement format. the table below shows the ideal codes: table 75. contact_check_dataout_1 (61h) bit name def. description 7 dummy 0 msb of cc_dataout. this register contains the most significant byte of the output data from the cont act check and it is readable when meas_mode=1 6 dummy 0 5 overcurr_p 0 4 overcurr_n 0 3 psmon1 0 2 psmon0 0 1 imp_overflow_flags 0 0 hc_overflow_flag3 0 table 76. contact_check_dataout_0 (62h) bit name def. description 7 hc_overflow_flag2 0 lsb of cc_dataout. this register c ontains the least significant byte of the output data from the cont act check and it is readable when meas_mode=1 6 hc_overflow_flag1 0 5 in_contact_out_flag6 0 4 in_contact_out_flag5 0 3 in_contact_out_flag4 0 2 in_contact_out_flag3 0 1 in_contact_out_flag2 0 0 in_contact_out_flag1 0
detailed description HM301D 70/85 docid026157 rev 4 the HM301D can send the processed data of biopotential channels and impedance channel or the raw data of the biopotential channels just after the first decimation filters (see figure 4). the data packet is different according to the type of data that is transmitted. 6.13.1 case 1: complete processed data - 4x packet in this case the packet will be formed by four word s of 16 bits each (base packet). in case of multi-chip configuration each device provides its own base packet. those base packets are organized in the following way. where the c_data can be a biopotential data vector or an impedance data vector or a miscellaneous data vector. in multi-chip config uration, the packet that the mcu receives contains first the header base packet for each device, then the c_data base packet for each device and so on. of course the first packet the mcu receives is sent by the last device in the chain and so on. for instance, if there are three devices in chain the order of the base packets inside the co mplete packet is: for every kind of configuration, every complete packet is updated with the lrhb channel path frequency. this frequency is function of the filters setting and can be 31.25 khz or 15.625 khz. in the following example we use the highest cut-off frequency (f c = 31.25 khz). therefore, in the case of three devices in ch ain, to correctly transfer all th e data from the devices to the mcu, a minimum serial clock frequency (fsck) is needed: f sck = n dev * l w * n pac * f pm = 3 * 16 * 4 * 31.25 khz = 6 mhz where: n dev : devices number in chain; table 77. data format input signal ideal output code v ref /gain 7fffh +v ref /gain/(2 15 -1) 0001h 0 0000h -v ref /gain/(2 15 -1) ffffh ? -v ref /gain/(2 15 -(2 15 -1) 8000h table 78. base pocket 16 bits 16 bits 16 bits 16 bits header c_data lrhb1_data lrhb2_data table 79. data packet out with 3 HM301D in chain heade r s3 heade r s2 heade r s1 c_dat a s3 c_dat a s2 c_dat a s1 lrhb1 s3 lrhb1 s2 lrhb1 s1 lrhb2 s3 lrhb s2 lrhb s1
docid026157 rev 4 71/85 HM301D detailed description 85 l w : word length; n pac : number of words per device. since the lrhb channel paths are updated with much lower frequency than the hrlb ones, there are some null vectors. another cont ribution to the null packets is given by if some channel is not used (e.g.: max number of pm signals per application). in order to have a more clear idea of the maxi mum number of useful packets, we have to consider that the minimum ratio between the lrhb frequency and the hrlb frequency is 32 (fpm = 31.25 khz) and the minimum ratio between the lrhb frequency and the impedance frequency is 200 (see par 0 for de tails). to get all the information about the biopotential channels we need to get 6 base packets (3 channels + 3 half-sums), therefore we obtain that 6 hrlb useful packets ev ery 32 complete pack ets will be transferred. for the impedance data, the device has to tran sfer 4 base_packets (iac, qac, idc, qdc), therefore 4 useful packets ever y 200 complete packets will be transferre d for the impedance channel. 6.13.2 case 2: pre-filter ed data out - 3x packet in this case the complete packet will be comp osed by 3 base_packets for each device in chain. the above me ntioned base_packets will be ordered in the following way: where: ch1, ch2 and ch3 are the 12 bits vectors at the first decimator output. of course if we have three devices in chain the packets w ill be ordered as the previous case. in this case, every device has to transfer three vectors of 12 bits. considering a configuration with 3 devices in chain the serial clock frequency (f sck ): needed to transfer a ll the data from the devices to the host is: f sck = n dev * lv * n pac * f prefilt = 3 * 16 * 3 * 125 khz = 18 mhz where: n dev : devices number in chain; l v : vectors length; n pac : packets number per device; f prefilt : pre-filtered data refresh frequency. in the case of 1 device: f sck = n dev * l v * n pac * f prefilt = 1 * 16 * 3 * 125 khz = 6 mhz so, in the case of 1 device with just 1 enabled channel: f sck = n dev * l v * n pac * f prefilt = 1 * 16 * 2 * 125 khz = 4 mhz this is the minimum serial clock frequency (fsck) needed to transfer a pre-filtered data vector for the minimum configuration (1 device with 1 enabled channel). table 80. pre-filtered data out 16 bits 16 bits 16 bits 12 bits 4 bits 8 bits 8 bits 4 bits 12 bits header <11:0> ch1 <11:8> ch1 <7:0> ch2 <11:4> ch2 <3:0> ch3 <11:0>
detailed description HM301D 72/85 docid026157 rev 4 6.13.3 header description the header packet contains the useful info to correctly interpret the whole packet meaning. the header packet is composed by 16bits in case 1 and by 12 bits in case 2: table 81. header packet bits description in 4x packet case header bits name description details 15:11 not used 10 lrhb2_en lrhb channel 2 data enable 9 lrhb1_en lrhb channel 1 data enable 8:7 num_dev <2:0> number devices in daisy chain configuration 00: 1 device 01: 2 devices 10: 3 devices 11: 4 devices 6 prefil_en pre-filtered data out enable 5pmd2 lrhb channel 2 data enable 4pmd1 lrhb channel 1data enable 3:0 c_data_desc <3:0> c_data description see ta ble 82 table 82. header packet bits description in 3x packet case header bits name description details 11:9 not used 8:7 num_dev <2:0> numbe r devices in daisy chain configuration 00: 1 device 01: 2 devices 10: 3 devices 11: 4 devices 6 prefil_en pre-filtered data out enable 5 lrhb2_en lrhb channel 2 data enable 4 lrhb1_en lrhb channel 1data enable 3:0 c_data_desc <3:0> c_data description see table 82
docid026157 rev 4 73/85 HM301D detailed description 85 the c_data packet contains different data a ccording to the c_data_desc. this is valid only for 4x packet case because in 3x packet case just the channels data is provided and without any filtering. when the c_data vector contains the contact check and overflow data, its 16 bits have the following meaning: table 83. c_data packet description bits configurations c_data_desc [3:0] c_data content 0000 no useful data in c_data vector 0001 ch1_hrlb data 0010 ch2_hrlb data 0011 ch3_hrlb data 0100 not used 0101 (ch1_hrlb + ch2_hrlb)/2 data 0110 (ch2_hrlb + ch3_hrlb)/2 data 0111 (ch3_hrlb + ch1_hrlb)/2 data 1000 zc dc_i data 1001 zc dc_q data 1010 zc ac_i data 1011 zc ac_q data 1100 contact check and overflow data (see table 82 ) 1101 not used 1110 not used 1111 not used table 84. contact check and overflow c_data vector contact check and overflow c_ data details [c_data_desc=1100] <15:0> description 15:14 not used 13 over_curr_p 12 over_curr_n 11:10 psmon 9 impedance channel overflow 8 ch3 overflow 7 ch2 overflow
detailed description HM301D 74/85 docid026157 rev 4 6.14 data rate the following two tables describe respectively the hrlb data-out sampling frequencies as function of the hrlb low pass filter cut-off frequency and the lrhb data-out sampling frequencies as function of the lrhb low pass filter cut-off frequency. also for the impedance channel the data rate is function of low pass filter cut-off frequency; table 87 provides the two sampling frequencies as function of low pass filter cut-off frequency. 6 ch1 overflow 5 in3n dc contact check 4 in3p dc contact check 3 in2n dc contact check 2 in2p dc contact check 1 in1n dc contact check 0 in1p dc contact check table 84. contact check and overflow c_data vector (continued) contact check and overflow c_ data details [c_data_desc=1100] <15:0> description table 85. hrlb data-out sampling frequency vs low pass filter cut-off frequency ciahrlb low pass fcut selector [hc_dig_ecglpf_sel_r] in set15 register low pass cut-off frequency (-3 db) sampling frequency hrlb data out 1000 600 hz 1.953 khz 0000 300 hz 0.976 khz 0001 200 hz 0.651 khz 0010 150 hz 0.488 khz 0011 100 hz 0.325 khz 0100 75 hz 0.244 khz 0101 50 hz 0.163 khz 0110 37 hz 0.122 khz 0111 25 hz 0.0815 khz table 86. lrhb data-out sampling frequency vs low pass filter cut-off frequency pm low pass f cut selector [hc_dig_pmlpf_sel_r] in set 16 register low pass cut-off frequency (-3 db) sampling frequency pm data out 0 10 khz 31.25 khz 1 5 khz 15.625 khz
docid026157 rev 4 75/85 HM301D detailed description 85 6.15 data ready operation the HM301D has two types of data ready and spi clock operation: packets data streaming and direct read command mode. these two procedures can be selected by meas_mode bit of set22 register (set22 <7>). one of the two ways can be used by choosing the proper signal as data ready in one of the dgios (refer to table 11 , table 12 and table 13 ). the packets data streaming method must be used if we are interested to retrieve the lrhb data; in this case the data ready signal to monitor is the pm_resh. if we are interested to read only the ecg data then the direct read command procedure must be selected and the da ta ready signal to monitor is the ecg_rsh. figure 21. spi communication - packet data streaming if meas_mode bit is zero, the packets data streaming operation is selected. in case of complete processed data the packet is composed by 4 words of 16 bits and the spi master must send at least 80 clock pulses only afte r the pm_resh signal goes high. the first 16 pulses are used by the HM301D to shift the da ta into the spi registers so sdo stays low. while with the other 64 clock pulses the mcu can retrieve the 64bits packet data ( figure 18 ). in case of pre-filtered data, the operation is exactly the same except for the fact that the packet is composed by 3 words bits so, just 64 and not 80 bits should be supplied by the mcu. in this case the right signal to be used as data ready is the prefilt_rsh which is output on dgio0 with dgio0_muxsel_r=1010 and on dgio1 with dgio1_muxsel_r=1001. in both cases the tdata_rshb is the set by the internal clock of the lrhb which can be 31.25 khz or 15.625 khz according to the low pass filter selection of the lrhb signal chain. if just the hrlb signals are of interest, the data can be retrieved using the spi data read command mode. to select this method the meas_mode bit must be asserted. in this case table 87. impedance data-out sampling frequency vs low pass filter cut-off frequency impedance low pass f cut selector [imp_dig_lpf_sel_r] in set19 register low pass cut-off frequency (-3 db) sampling frequency impedance data out 0 1 hz 7.8 hz 1 20 hz 156 hz
detailed description HM301D 76/85 docid026157 rev 4 the ecg_rsh must be used as trigger signal, so when ecg_rsh goes high the microcontroller must directly read the ecg_out registers using the direct word reading procedure as described in figure 19 . this ecg_rsh signal is available at dgio2 with dgio2_muxsel_r=1010. figure 22. ecg_out registers data reading spc cs 32 bits sdi r / w a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 r / w a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 sdo d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r / w a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 r / w a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 r / w a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ecg_rsh
docid026157 rev 4 77/85 HM301D application information 85 7 application information 7.1 dc offset removal the electrode half-cell potential acts as a dc offset voltage on each of the incoming electrode signals and, depending on the applic ation, also on the outgoing rld electrode signal. in the biopotential channels and in the impedance channel the dc component is removed by the high pass filters. the maximum half cell potential (dc_os) the device can handle is defined by the supply voltage and by the rld reference voltage rlf_vref. since the dc value is removed at the inputs of each acquisition channel, the limiting building block is the ou tput swing of the rld buffer which is limited by the supply voltage. the output swing toward s vss is limited by the difference between vref and vss. the outp ut swing towards vdd is limited by the difference between vdd and rlf_vref. the worst case situation is when a ll half-cell potentials are in the same direction, i.e. positive or negative. in this case from the rld output buffer towards the input of the health channel two half-cell potentials have to be subtracted. according to the medical standard, the rld has to deliver 880 na peak current. this gives an additional voltage drop of 264 mv over the dc current limiting resistor of the rld. so t he maximum output swing the rld node (after the internal resi stor) is vss+325 mv and vdd-350 mv. taking all signals into account, the maximum dc offset can be calculat ed as the minimum of the following two equations: equation 3 equation 4 for higher vdd, dcos vdd increases while dcos vss stays the same. so, at high vdd, it is beneficial to increase the rld reference voltage rld_vref voltage in order to cope with higher dc offset. the bits rld_ref_sel_r change the rld reference voltage to 0.7 v, 1.0 v and 1.49 v. figure 23 shows the maximal electrode offset versus supply for different reference voltages. ) 325 . 0 ( _ ? ? ? vss vref rld dcos vss vref rld vdd dcos vdd _ ) 350 . 0 ( ? ? ?
application information HM301D 78/85 docid026157 rev 4 figure 23. maximum dc offset removal 7.2 multi-chip configuration in order to build a system supporting more than 3 biopotential channels, the HM301D can be used in a multiple chip configuration. in this configuration the spi will be configured as daisy chai ned spi by connecting the data output of one device to the data input of anot her. the first and the last devices of the chain will be connected to the mcu. the maximum number of devic es that can be connected together is 4. one of the HM301D chip can be used as analo g master in the system: it distributes the wct signal, drives the shield and right leg and sends out its clock signal to the others. figure 24 shows an example of 3 HM301D c onnected together for 12 leads ecg application. am17593v1 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.61.8 2 2.22.42.62.8 3 3.23.43.6 dc offset [v] avdd [v] vref = 0.7 v vref = 1.0 v vref = 1.49 v
docid026157 rev 4 79/85 HM301D application information 85 figure 24. example of chain connection: standard 12-lead ecg in multi-chip configuration th e data send and received by the mcu through the spi are formatted in a different way compared to single chip configuration. am17594v2 cs spc sdi sdo ckext avg vref sd rld wct in2p in2n in1n in1p cs spc sdi sdo ckext avg vref in2p in2n in1n in1p sd rld wct in3n in3p cs spc sdi sdo ckext avg vref in2p in2n in1n in1p sd rld wct in3n in3p miso mosi sck ss l ll r rl v1 v4 v5 v6 v2 v3 shield HM301D HM301D HM301D mcu
application information HM301D 80/85 docid026157 rev 4 7.3 supported ecg configurations even if designed for any type of biopotential ac quisition, the HM301D is particularly suited to ecg systems. to address most possible applic ations, each channel of the HM301D can be connected to the electrodes either as bipolar or unipolar. at the output of the channel, the bipolar co nfiguration gives the difference between 2 electrodes. otherwise, the unipolar configurat ion reads the difference between the single electrode voltage and a reference voltage (the internal reference or wct from the same chip or from the master chip in a chain connection). as an example the standard 12-lead electr ocardiogram application is shown in figure 24 . it requires the measurement of 12 differential sign als, exploiting 9 electrodes. 8 differential channels are obtained by cascading 3 HM301D. the master (ic in the top) is connected to the 3 limb electrodes using a bipolar connectio n for both channels. it provides a wct signal, clock timing and drives the rl electrode. hm3 01d devices, configured as unipolar, measure all 6 chest electrodes with respect to wct. combining the resulting 8 outputs, all 12 standards leads can be evaluated. table 88. common ecg configurations application electrodes connection channels device standards 12 leads ecg 9 + rl 2 bipolar + 6 unipolar 8 3x HM301D standards 12 leads ecg 9 + rl 9 unipolar 9 3x HM301D interpolated 12 leads using a 6 wires cable 5 + rl 2 bipolar + 2 unipolar 4 2x HM301D interpolated 12 leads using a 6 wires cable 5 + rl 5 unipolar 5 2x HM301D 5 leads wire / easi 4 + rl 2 bi polar + 1 unipolar 3 1x HM301D 5 leads wire / easi 4 + rl 4 unipolar 4 2x HM301D einthoven?s triangle 3 + rl 2 bipolar 2 1x HM301D einthoven?s triangle 3 + rl 3 unipolar 2 1x HM301D rhythm 2 1 bipolar 1 1x HM301D automated external defibrillator (aed) 2 1 bipolar 1 1x HM301D
docid026157 rev 4 81/85 HM301D package mechanical data 85 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data HM301D 82/85 docid026157 rev 4 figure 25. package outline for lga 40l (6 x 6 mm)
docid026157 rev 4 83/85 HM301D package mechanical data 85 table 89. lga 40l (6 x 6 mm) mechanical data symbol (mm) min. typ. max. a1 0.810 0.900 0.960 a2 0.660 0.700 0.710 a3 0.150 0.200 0.250 d1 5.850 6.000 6150 e1 5.850 6.000 6150 l1 4.460 4.500 4.540 l2 4.460 4.500 4.540 n1 0.460 0.500 0.540 n2 0.210 0.250 0.290 m 0.060 0.100 0.140 p1 2.690 2.730 2.77 p2 2.690 2.730 2.77 t1 0.310 0.350 0.390 t2 0.310 0.350 0.390 d 0.210 0.250 0.290 k0.050
revision history HM301D 84/85 docid026157 rev 4 9 revision history table 90. document revision history date revision changes 01-apr-2014 1 initial release 11-apr-2014 2 updated order code table 1 on page 1 14-may-2014 3 changed unit odr parameter table 5 on page 12 01-jul-2014 4 updated name table 58 on page 63
docid026157 rev 4 85/85 HM301D 85 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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